Synchronous/asynchronous i/o channel check and parity check detector

Claim 1

In a personal computer having a first parity detector for detecting parity errors while transferring data in a memory and generating PARITY ERROR signals in response thereto, and a second parity detector for detecting parity errors while transferring data in an I/O channel and generating I/O CHAN CHK signals in response thereto, and an I/O controller for receiving said PARITY ERROR signals and said I/O CHAN CHK signals, said controller comprising an I/O channel check and parity check detector comprising: a parity check detector having a first input line connected to receive said PARITY ERROR signals; a channel check detector having a second input line connected to receive said I/O CHAN CHK signals, said channel check detector being also connected to said first input line to receive said PARITY ERROR signals ; first and second read back registers; first and second glitch reject circuits connected between said detectors and said read back registers for transmitting pulses from said detectors to said registers which pulses have widths greater than a predetermined value and rejecting pulses from said detectors having widths less than said predetermined value; said first read back register having a first latch settable in response to receiving a pulse from said first glitch reject circuit to provide a read back bit signifying receipt of an I/O CHAN CHK signal by said channel detector; and said second read back register having a first latch settable in response to receiving a pulse from said second glitch reject circuit to provide a read back bit signifying receipt of an PARITY ERROR signal by said parity error detector.