US4530095A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Comparison of digital bit streams using modified parity
Assignee: Nokia Bell Labs
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Filing: 1983-03-09
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Granted: 1985-07-16
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Expires: 2003-03-09
Abstract
Abstract A modified parity calculation technique is presented which obviates the conventional requirement of deterministically inserting markers into a bit stream of data. The advantages of the present technique are fully realized in applications for in-service monitoring of extremely high speed bit streams of data. A bit pattern, or template, is compared to the content of the bit stream to detect matches between the two. The matches determine bit spans on which the parity calculation is performed. Since the parity signal is highly compressed and low speed relative to the data, it can be readily delayed to facilitate confirmation of identical content of two high speed bit streams which differ substantially in relative timing.
Inventors
- 👤 Clarke S. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:32
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H04; H04L; H04L1/00; H04L1/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
Apparatus for producing a parity calculation on a bit stream of data, the apparatus comprising: means for storing a predetermined bit pattern, means for comparing the predetermined bit pattern to the bit stream of data and for generating a match output signal indicating the occurrence of each match, and parity counting means, responsive to the match output signal and to the bit stream of data, for doing a parity count between occurrences of the match output signal and for producing a first parity signal indicative of the parity state of each parity counting calculation.
Claim 2
Dependent Claim
94 words
Apparatus for producing a parity calculation on a bit stream of data, the apparatus comprising: means for storing a predetermined bit pattern, means for comparing the predetermined bit pattern to the bit stream of data and for generating a match output signal indicating the occurrence of each match, and parity counting means, responsive to the match output signal and to the bit stream of data, for doing a parity count between occurrences of the match output signal and for producing a first parity signal indicative of the parity state of each parity counting calculation.
Claim 3
Dependent Claim
90 words
The apparatus as defined in claim 1 wherein the parity counting means further includes counting means responsive to a parity clocking signal for generating an inhibit signal to establish a minimum span interval of data on which the parity calculation is being performed, and gating means having two inputs and the inhibit signal being supplied to one of the inputs and the match output signal being supplied to the other one of the inputs for generating the parity clocking signal, wherein the parity clocking signal clears the parity counting means.
Claim 4
Dependent Claim
76 words
Apparatus in accordance with claim 2 further comprising: switching means for selecting one of two input signals, the first input signal being a predetermined number of successive bits from the bit stream and the second input signal being a signal indicative of a predetermined bit pattern, and wherein the means for storing includes register means connected to the output of the switching means for storing the selected input to be used as the predetermined bit pattern.
Claim 5
Dependent Claim
220 words
Apparatus for generating an error indication between two data streams comprising: first and second parity calculating circuitry for generating first and second parity indicating signals and first and second parity clocking signals, respectively, each of the parity calculating circuitry including means for storing a predetermined bit pattern, means for comparing the stored predetermined bit pattern to a corresponding one of the data streams and for generating a match output signal indicating the occurrence of each match, and parity counting means, responsive to the match output signal and to the corresponding bit stream of data, for doing a parity count between occurrences of the match output signal and for producing a parity signal indicative of the parity state of each parity counting calculation for the corresponding bit stream; means for controllably delaying one of the parity indicating signals relative to the other parity indicating signal so that the first and second parity indicating signals are in alignment; comparing means supplied with the delayed parity indicating signal and the other nondelayed parity indicating signal for generating an error signal when the parity indicating signals are out of alignment; and means responsive to the error signal for controlling the delaying means, wherein the occurrence of the error signal is minimized and thereby alignment of the first and second parity indicating signals is obtained.
Claim 6
Dependent Claim
220 words
Apparatus for generating an error indication between two data streams comprising: first and second parity calculating circuitry for generating first and second parity indicating signals and first and second parity clocking signals, respectively, each of the parity calculating circuitry including means for storing a predetermined bit pattern, means for comparing the stored predetermined bit pattern to a corresponding one of the data streams and for generating a match output signal indicating the occurrence of each match, and parity counting means, responsive to the match output signal and to the corresponding bit stream of data, for doing a parity count between occurrences of the match output signal and for producing a parity signal indicative of the parity state of each parity counting calculation for the corresponding bit stream; means for controllably delaying one of the parity indicating signals relative to the other parity indicating signal so that the first and second parity indicating signals are in alignment; comparing means supplied with the delayed parity indicating signal and the other nondelayed parity indicating signal for generating an error signal when the parity indicating signals are out of alignment; and means responsive to the error signal for controlling the delaying means, wherein the occurrence of the error signal is minimized and thereby alignment of the first and second parity indicating signals is obtained.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |