US5033050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Operation control system
Assignee: Toshiba Corp
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Filing: 1989-03-20
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Granted: 1991-07-16
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Expires: 2009-03-20
Abstract
Abstract A data processing system having a device performing input and output of data for processing the data. The system includes a main control unit for processing the data and for performing a parity check function to detect abnormality of data transmitted in the system, a parity check control unit coupled to the main control unit for performing the parity check function for the device, and an external device unit operative coupled to the main control unit and the parity check control unit for performing input and output of the data under control of the parity check function and for generating an inhibition signal to inhibit the operation of the parity check control unit.
Inventors
- 👤 Michio Murai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
137 words
A data processing system having a plurality of devices, interconnected by an external bus, for processing data subject to a parity error detection function, comprising: main control device means, coupled to the external bus, for processing data, for transmitting and receiving data over the external bus, and for performing a parity check operation; parity check control device means coupled to the external bus and the main control device means, and responsive to an inhibition signal for selectively performing a parity check function on data appearing on the external bus; and external device means coupled to the external bus, the main control device means, and the parity check control device means for transmitting and receiving data over the external bus, for performing input and output of data, and for selectively generating the inhibition signal according to predetermined criteria.
Claim 2
Dependent Claim
137 words
A data processing system having a plurality of devices, interconnected by an external bus, for processing data subject to a parity error detection function, comprising: main control device means, coupled to the external bus, for processing data, for transmitting and receiving data over the external bus, and for performing a parity check operation; parity check control device means coupled to the external bus and the main control device means, and responsive to an inhibition signal for selectively performing a parity check function on data appearing on the external bus; and external device means coupled to the external bus, the main control device means, and the parity check control device means for transmitting and receiving data over the external bus, for performing input and output of data, and for selectively generating the inhibition signal according to predetermined criteria.
Claim 3
Dependent Claim
62 words
The system of claim 1 wherein the main control means includes means for generating output and collection commands; and wherein the parity check control device means includes means responsive to the output command and the inhibition signal for selectively performing a parity check operation and means responsive to the collection command and the inhibition signal for selectively performing a parity generation operation.
Claim 4
Dependent Claim
41 words
The system of claim 1 wherein the parity check control means includes parity check means for performing a parity check operation, and parity control means for inhibiting the operation of the parity check control means in response to the inhibition signal.
Claim 5
Dependent Claim
29 words
The system of claim 1 wherein the external device means includes parity check means for performing a parity check operation, and parity inhibition means for generating the inhibition signal.
Claim 6
Dependent Claim
51 words
The system of claim 1 wherein the main control means and the external device each include means for performing a parity error detection function, and wherein the external device means generates the inhibition signal when the main control device means and the external device means have different parity error detection functions.
Claim 7
Dependent Claim
42 words
The system of claim 1 wherein the external device means comprises inhibitable means for performing a parity error detection function, and wherein the external device means generates the inhibition signal when the means for performing a parity error detection function is inhibited.
Claim 8
Independent Claim
126 words
A method for processing data subject to a parity error detection function in a data processing system having a plurality of devices interconnected by an external bus for processing data, comprising: processing data in a main control device coupled to the external bus; selectively performing, in response to an inhibition signal, a parity check function in a parity check control device coupled to the external bus and the main control device on data appearing on the external bus; performing input and output of data transmitted and received over the external bus by an external means coupled to the external bus, the main control device means, and the parity check control device means; and selectively generating the inhibition signal in the external device according to predetermined criteria.
Claim 9
Independent Claim
126 words
A method for processing data subject to a parity error detection function in a data processing system having a plurality of devices interconnected by an external bus for processing data, comprising: processing data in a main control device coupled to the external bus; selectively performing, in response to an inhibition signal, a parity check function in a parity check control device coupled to the external bus and the main control device on data appearing on the external bus; performing input and output of data transmitted and received over the external bus by an external means coupled to the external bus, the main control device means, and the parity check control device means; and selectively generating the inhibition signal in the external device according to predetermined criteria.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |