Current mode driver for differential bus

Claim 2

A current mode bus driver for coupling input digital logic signals to a bus consisting of two signal leads, said bus driver comprising means for providing a current source, means for providing a current sink, means responsive to an input digital logic signal of one binary type for coupling said current source means to one of said two signal leads and said current sink means to the other of said two signal leads, and means responsive to an input digital logic signal of the other binary type for coupling said current source means to said current sink means.

Claim 3

A current mode bus driver as defined in claim 1 wherein said means for coupling said current source means to one of said two signal leads and said current sink means to the other of said two signal leads includes a first and second metal oxide semiconductor field effect transistor (MOSFET) each of which has a source, drain and gate electrode, said first MOSFET having its drain and source electrodes connected between said current source means and the one of said two signal leads, said second MOSFET having its drain and source electrodes connected between said current sink means and the other of said two signal leads, and means for selectively coupling said input digital logic signals to the gate electrodes of said first and second MOSFETs.

Claim 4

A current mode bus driver as defined in claim 2 wherein said means for coupling said current source means to said current sink means includes third and fourth MOSFETs each of which has a source, drain and collector electrode, means for connecting said drain and source electrodes of said third and fourth MOSFETs in series with said current source means and said current sink means with the source of said third MOSFET being directly connected to the drain of said fourth MOSFET, and means for selectively coupling said input digital logic signals to the gate electrodes of said third and fourth MOSFETs.

Claim 5

A current mode bus driver as defined in claim 3 wherein said means for selectively coupling said input digital logic signals to the gate electrodes of said first and second MOSFETs includes a pair of buffer driver circuits each one of which comprises a complementary metal oxide semiconductor (CMOS) inverter having an input and an output, means for coupling said input digital logic signals to the input of said CMOS inverter, an NPN transistor having emitter, base and collector electrodes with its collector electrode connected receive to a positive potential source and its base electrode connected to the output of said CMOS inverter, an n-channel MOSFET having drain, source and gate electrodes, the drain electrode of said n-channel MOSFET being connected to the emitter electrode of said NPN transistor, the source electrode of said n-channel MOSFET being connected to receive a ground potential, and the gate electrode of said n-channel MOSFET being connected to the input of said CMOS inverter.

Claim 6

A current mode bus driver for coupling input digital logic signals to a bus consisting of two signal leads, said bus driver comprising means for providing a current source, means for providing a current sink, and selective switching means having two control inputs connected to receive said input digital logic signals for coupling said current source means to one of said two signal leads and said current sink means to the other one of said two signal leads in response to an input digital logic signal of only one binary type; said selective switching means including first and second metal oxide semiconductor field effect transistor (MOSFET) each of which has a source, drain and gate electrode, said first MOSFET having its drain and source electrodes connected between said current source means and the one of said two signal leads, said second MOSFET having its drain and source electrodes connected between said current sink means and the other of said two signal leads, means for selectively coupling said input digital logic signals to the gate electrodes of said first and second MOSFETs, third and fourth MOSFETs each of which has a source, drain and collector electrode, means for connecting said drain and source electrodes of said third and fourth MOSFETs in series with said current source means and said current sink means with the source of said third MOSFET being directly connected to the drain of said fourth MOSFET, and means for selectively coupling said input digital logic signals to the gate electrodes of said third and fourth MOSFETs.

Claim 7

A current mode bus driver for coupling input digital logic signals to a bus consisting of two signal leads, said bus driver comprising means for providing a current source, means for providing a current sink, and selective switching means having two control inputs connected to receive said input digital logic signals for coupling said current source means to one of said two signal leads and said current sink means to the other one of said two signal leads in response to an input digital logic signal of only one binary type; said selective switching means including first and second metal oxide semiconductor field effect transistor (MOSFET) each of which has a source, drain and gate electrode, said first MOSFET having its drain and source electrodes connected between said current source means and the one of said two signal leads, said second MOSFET having its drain and source electrodes connected between said current sink means and the other of said two signal leads, means for selectively coupling said input digital logic signals to the gate electrodes of said first and second MOSFETs, third and fourth MOSFETs each of which has a source, drain and collector electrode, means for connecting said drain and source electrodes of said third and fourth MOSFETs in series with said current source means and said current sink means with the source of said third MOSFET being directly connected to the drain of said fourth MOSFET, and means for selectively coupling said input digital logic signals to the gate electrodes of said third and fourth MOSFETs.

Claim 8

A current mode bus driver as defined in claim 5 wherein said means for selectively coupling said input digital logic signals to the gate electrodes of said first and second MOSFETs includes a pair of buffer driver circuits each one of which includes a complementary metal oxide semiconductor (CMOS) inverter having an input and an output, means for coupling said input digital logic signals to the input of said CMOS inverter, an NPN transistor having emitter, base and collector electrodes with its collector electrode connected to receive a positive potential source and its base electrode connected to the output of said CMOS inverter, an n-channel MOSFET having drain, source and gate electrodes, the drain electrode of said n-channel MOSFET being connected to the emitter electrode of said NPN transistor, the source electrode of said n-channel MOSFET being connected to a ground potential, and the gate electrode of said n-channel MOSFET being connected to the input of said CMOS inverter.

Claim 9

A current mode bus driver as defined in claims 1 or 5 wherein said current source means comprises a first p-channel MOSFET having a drain, source and gate electrode, an NPN transistor having an emitter, base and collector electrodes, a resistive element connected between said emitter electrode and a ground potential, means for connecting a reference potential to the base electrode of said NPN transistor, and means for connecting said source electrode to a potential source, means for directly connecting said drain and gate electrodes to said collector electrode whereby a reference current is established out of said drain and into the collector of said collector electrode, a second p-channel MOSFET having a drain, source and gate electrode, means for connecting the drain of said second MOSFET to said potential source, and means for directly connecting the gate of said second p-channel MOSFET to the gate of said first p-channel MOSFET whereby a source of current is established at the drain electrode of said second p-channel MOSFET.

Claim 10

A current mode bus driver as defined in claim 7 wherein said current sink comprises a third p-channel MOSFET having a source, drain and gate electrode, means for connecting the source of said third p-channel MOSFET to said potential source, means for connecting the gate of said third MOSFET to the gate of said first MOSFET, a second NPN transistor having emitter, base and collector electrodes, a second resistive element connected between the emitter electrode of said second transistor and said ground potential, means for directly connecting the collector electrode of said second transistor to the drain of said third MOSFET, a third NPN transistor having its base connected to the drain of said third MOSFET and its emitter connected to the base of said second transistor, the collector of said third transistor being connected to said potential source, a third resistive element, and a fourth NPN transistor having its emitter connected through said third resistive element to ground and its base electrode connected to the base electrode of said second transistor, whereby the collector of said fourth transistor provides a sink of current relative to said ground potential.