US4864159A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL to CMOS transition amplifier
Assignee: US Philips Corp
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Filing: 1988-08-25
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Granted: 1989-09-05
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Expires: 2008-08-25
Abstract
Abstract When processing logic signals in ECL and CMOS circuitry it is necessary to adjust the logic levels when going from one type of circuitry to another. A problem which occurs is that smearing of a logic level occurs due to poor rise and fall times in a level adjusting amplifier. The rise and fall times can be improved by the level adjusting amplifier load circuit comprising the series connection of the source-drain paths of first and second N-channel transistors (20, 22), the parasitic capacitance of the drain of the first transistor (20) at a node (23), and by connecting the gate of the second transistor (22) to the node. In operation, when the first transistor (20) is non-conductive and the node (23) is charged, the second transistor (22) is operating in the triode or linear region of its characteristic in spite of its gate being at the voltage of the node. When the first transistor (20) is rendered conductive then both transistors (20, 22) are fully conductive and the starting discharge current is high. An amplifier including a symmetrical load is disclosed in FIG. 4.
Inventors
- 👤 Bernardus H. J. Cornelissen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:20
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03F3/00; H03F3/26; H03F3/265
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
294 words
A symmetrical amplifier load circuit comprising first and second parallel arranged branches coupled between first and second supply voltage lines, a first input circuit, a second input circuit, a first output stage, and a seocnd output stage, wherein the first branch comprises first and second field effect transistors (FETs) of similar conductivity type having gate, source and drain electrodes, the source-drain paths of the first and second field effect transistors being connected in series and with the drain of the first field effect transistor coupled via the first input circuit to the first supply voltage line and the source of the second field effect transistor coupled to the second supply voltage line, a parasitic capacitance of the drain of the first field effect transistor providing a first node, the gate of the second field effect transistor being connected to the first node which is also connected to the first output stage, and wherein the second branch comprises third and fourth FETs of the same conductivity type as the first and second FETs and having gate, source and drain electrodes, the source-drain paths of the third and fourth FETs being connected in series and with the drain of the third field effect transistor coupled via the second input circuit to the first supply voltage line and the source of the fourth FET coupled to the second supply voltage line, a parasitic capacitance of the drain of the third FET providing a second node, the gate of the fourth FET being connected to the second node which is also connected to the second output stage, the drain of the third FET being connected to the gate of the first FET and the gate of the third FET being connected to the drain of the first FET.
Claim 2
Dependent Claim
294 words
A symmetrical amplifier load circuit comprising first and second parallel arranged branches coupled between first and second supply voltage lines, a first input circuit, a second input circuit, a first output stage, and a seocnd output stage, wherein the first branch comprises first and second field effect transistors (FETs) of similar conductivity type having gate, source and drain electrodes, the source-drain paths of the first and second field effect transistors being connected in series and with the drain of the first field effect transistor coupled via the first input circuit to the first supply voltage line and the source of the second field effect transistor coupled to the second supply voltage line, a parasitic capacitance of the drain of the first field effect transistor providing a first node, the gate of the second field effect transistor being connected to the first node which is also connected to the first output stage, and wherein the second branch comprises third and fourth FETs of the same conductivity type as the first and second FETs and having gate, source and drain electrodes, the source-drain paths of the third and fourth FETs being connected in series and with the drain of the third field effect transistor coupled via the second input circuit to the first supply voltage line and the source of the fourth FET coupled to the second supply voltage line, a parasitic capacitance of the drain of the third FET providing a second node, the gate of the fourth FET being connected to the second node which is also connected to the second output stage, the drain of the third FET being connected to the gate of the first FET and the gate of the third FET being connected to the drain of the first FET.
Claim 3
Dependent Claim
17 words
A circuit as claimed in claim 1, wherein the first, second, third and fourth FETs are N-FETs.
Claim 4
Dependent Claim
22 words
A circuit as claimed in claim 2, wherein the first and second input circuits comprise first and second emitter follower circuits, respectively.
Claim 5
Dependent Claim
22 words
A circuit as claimed in claim 1, wherein the first and second input circuits comprise first and second emitter follower circuits, respectively.
Claim 6
Dependent Claim
49 words
A circuit as claimed in claim 4, wherein a first P-FET has its source-drain path connected between the emitter of the first emitter follower and the first node and a second P-FET has its sourcedrain path connected between the emitter of the second emitter follower and the second node.
Claim 7
Dependent Claim
350 words
An amplifier for adjusting logic levels used in ECL logic to logic levels used in CMOS logic, comprising first and second parallel arranged branches coupled between first and second supply voltage lines, the first branch comprising a first NPN transistor connected as an emitter follower having its collector electrode connected to the first supply voltage line, its base electrode connected to a first input signal source and its emitter electrode connected to the source of a first P-channel FET (P-FET) connected in common gate configuration, and first and second N-channel FETs (N-FET) having their source-drain paths connected in series between a drain of the first P-FET and the second supply voltage line, a junction of the drains of the first P-FET and the first N-FET constituting a first node, the second branch comprising a second NPN transistor connected as an emitter follower having its collector electrode connected to the first supply voltage line, its base electrode connected to a second input signal source and its emitter connected to the source of a second P-FET connected in common gate configuration, and third and fourth N-FETs having their source-drain paths connected in series between a drain of the second P-FET and the second supply voltage line, a junction of the drains of the second P-FET and the third N-FEt constituting a second node, a first output stage comprising a third P-FET in DC-biased gate configuration having its source-drain path connected in series with that of a fifth N-FET between the emitter of the first NPN transistor and the second supply voltage line, and a second output stage comprising a fourth P-FET in DC-biased gate configuration having its source-drain path connected in series with that of a sixth N-FET between the emitter of the second NPN transistor and the second supply voltage line, the gate electrodes of the second, third and sixth N-FETs being connected to the first node, the gate electrodes of the first, fourth and fifth N-FETs being connected to the second node, and the gates of the first, second, third and fourth P-FETs being connected to a bias voltage supply.
Claim 8
Dependent Claim
350 words
An amplifier for adjusting logic levels used in ECL logic to logic levels used in CMOS logic, comprising first and second parallel arranged branches coupled between first and second supply voltage lines, the first branch comprising a first NPN transistor connected as an emitter follower having its collector electrode connected to the first supply voltage line, its base electrode connected to a first input signal source and its emitter electrode connected to the source of a first P-channel FET (P-FET) connected in common gate configuration, and first and second N-channel FETs (N-FET) having their source-drain paths connected in series between a drain of the first P-FET and the second supply voltage line, a junction of the drains of the first P-FET and the first N-FET constituting a first node, the second branch comprising a second NPN transistor connected as an emitter follower having its collector electrode connected to the first supply voltage line, its base electrode connected to a second input signal source and its emitter connected to the source of a second P-FET connected in common gate configuration, and third and fourth N-FETs having their source-drain paths connected in series between a drain of the second P-FET and the second supply voltage line, a junction of the drains of the second P-FET and the third N-FEt constituting a second node, a first output stage comprising a third P-FET in DC-biased gate configuration having its source-drain path connected in series with that of a fifth N-FET between the emitter of the first NPN transistor and the second supply voltage line, and a second output stage comprising a fourth P-FET in DC-biased gate configuration having its source-drain path connected in series with that of a sixth N-FET between the emitter of the second NPN transistor and the second supply voltage line, the gate electrodes of the second, third and sixth N-FETs being connected to the first node, the gate electrodes of the first, fourth and fifth N-FETs being connected to the second node, and the gates of the first, second, third and fourth P-FETs being connected to a bias voltage supply.
Claim 9
Dependent Claim
23 words
An amplifier as claimed in claim 6, wherein back-gates of the first and second P-FETs are connected to the first supply voltage line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-04 | 1993-03-06 | 1993-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-04 | 1997-03-06 | 1997-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-04 | 2001-03-06 | 2001-09-05 | $7700.00 | Window Closed / Lapsed |