High voltage CMOS circuit

Claim 2

A CMOS monolithic integrated circuit having high voltage capability, comprising: a P channel field effect transistor having a first electrode, a second electrode and a gate electrode, the first electrode capable of being coupled to a first voltage potential; a first N channel field effect transistor having a first and a second electrode and a gate electrode, the first electrode of the first N channel transistor being coupled to the second electrode of the P channel transistor and forming an output junction for the circuit; a second N channel field effect transistor having a first and a second electrode and a gate electrode, the first electrode of the second N channel transistor being coupled to the second electrode of the first N channel transistor, the second electrode of the second N channel transistor being capable of being coupled to a second voltage potential, each of said first and second N channel field effect transistors having a tub and wherein each tub is connected to the second electrode of each respective transistor, and the gate electrodes of the P channel and first and second N channel transistors all being coupled together; and a level shift means for providing a voltage level shift to an input voltage, the level shift means providing an output coupled to the gate electrodes of the P channel and first and second N channel transistors.

Claim 3

A CMOS monolithic integrated inverter circuit having high voltage capability, comprising: a P channel transistor; and a first and second N channel transistor, the P channel and the first and second N channel transistors all being coupled in series and all the transistors having gate electrodes connected together and forming an input for the inverter circuit, an output for the circuit comprising the connection between the P channel transistor and the first N channel transistor, the first and second N channel transistors each having a separate P tub.

Claim 4

A CMOS monolithic integrated inverter circuit having high voltage capability, comprising: a P channel transistor; and a first and second N channel transistor, the P channel and the first and second N channel transistors all being coupled in series and all the transistors having gate electrodes connected together and forming an input for the inverter circuit, an output for the circuit comprising the connection between the P channel transistor and the first N channel transistor, the first and second N channel transistors each having a separate P tub.

Claim 5

A CMOS circuit having high voltage capability and being able to provide a voltage level shift, comprising: a first N channel transistor having a first and a second electrode and a gate electrode, the gate electrode being coupled to the first electrode; a second N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the second N channel transistor being coupled to the second electrode of the first N channel transistor, the second electrode of the second N channel transistor being connectable to a first voltage potential terminal, the gate electrode of the second N channel transistor being coupled to the gate electrode of the first transistor; means for providing a resistance coupled between the first electrode of the first N channel transistor and a second voltage potential terminal; a P channel transistor coupled between the second voltage potential and an output node and having a gate electrode for receiving an input to the circuit; a third N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the third N channel transistor being coupled to the output node, the gate electrode of the third N channel transistor being coupled to the gate electrode of the first N channel transistor; and a fourth N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the fourth N channel transistor being coupled to the second electrode of the third N channel transistor, the second electrode of the fourth N channel transistor being coupled to the first voltage potential terminal, each of the N channel transistors having a separate tub and each tub being connected to a respective second electrode.

Claim 6

A CMOS circuit having high voltage capability and being able to provide a voltage level shift, comprising: a first N channel transistor having a first and a second electrode and a gate electrode, the gate electrode being coupled to the first electrode; a second N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the second N channel transistor being coupled to the second electrode of the first N channel transistor, the second electrode of the second N channel transistor being connectable to a first voltage potential terminal, the gate electrode of the second N channel transistor being coupled to the gate electrode of the first transistor; means for providing a resistance coupled between the first electrode of the first N channel transistor and a second voltage potential terminal; a P channel transistor coupled between the second voltage potential and an output node and having a gate electrode for receiving an input to the circuit; a third N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the third N channel transistor being coupled to the output node, the gate electrode of the third N channel transistor being coupled to the gate electrode of the first N channel transistor; and a fourth N channel transistor having a first and a second electrode and a gate electrode, the first electrode of the fourth N channel transistor being coupled to the second electrode of the third N channel transistor, the second electrode of the fourth N channel transistor being coupled to the first voltage potential terminal, each of the N channel transistors having a separate tub and each tub being connected to a respective second electrode.

Claim 7

A CMOS circuit having high voltage capability and providing a voltage level shift between an input and an output of the circuit comprising: a first P channel transistor coupled between a first voltage potential terminal and a first node and having a gate electrode coupled to the input of the circuit; a first and a second N channel transistor coupled in series between the first node and a second voltage potential terminal and having gate electrodes coupled to the output of the circuit; a second P channel transistor coupled between the first voltage potential terminal and the output and having a gate electrode for receiving a complement of a signal receivable by the input of the circuit; and a third and fourth N channel transistor coupled in series between the output and the second voltage potential terminal and having gate electrodes coupled to the first node, each N channel transistor having a separate tub which is connected to a source of its respective transistor.

Claim 8

A CMOS circuit having high voltage capability and providing a voltage level shift between an input and an output of the circuit comprising: a first P channel transistor coupled between a first voltage potential terminal and a first node and having a gate electrode coupled to the input of the circuit; a first and a second N channel transistor coupled in series between the first node and a second voltage potential terminal and having gate electrodes coupled to the output of the circuit; a second P channel transistor coupled between the first voltage potential terminal and the output and having a gate electrode for receiving a complement of a signal receivable by the input of the circuit; and a third and fourth N channel transistor coupled in series between the output and the second voltage potential terminal and having gate electrodes coupled to the first node, each N channel transistor having a separate tub which is connected to a source of its respective transistor.

Claim 9

A CMOS circuit having high voltage capability and capable of performing a logic gate function and having at least a first and a second input and an output, comprising: a first and a second P channel transistor coupled in series between a first voltage potential node and the output, each P channel transistor having a gate electrode serving as an input for the circuit; a first and second N channel transistor coupled in series between the output and a second voltage potential node and having gate electrodes coupled to the first input of the circuit; and a third and fourth N channel transistor coupled in series between the output and the second voltage potential node and having gate electrodes coupled to the second input of the circuit, each of the N channel transistors having a separate tub connected to a source of the respective N channel transistor.

Claim 10

A CMOS circuit having high voltage capability and capable of performing a logic gate function and having at least a first and a second input and an output, comprising: a first and a second P channel transistor coupled in series between a first voltage potential node and the output, each P channel transistor having a gate electrode serving as an input for the circuit; a first and second N channel transistor coupled in series between the output and a second voltage potential node and having gate electrodes coupled to the first input of the circuit; and a third and fourth N channel transistor coupled in series between the output and the second voltage potential node and having gate electrodes coupled to the second input of the circuit, each of the N channel transistors having a separate tub connected to a source of the respective N channel transistor.

Claim 11

A CMOS circuit having high voltage capability and having at least a first and a second input and an output and being capable of performing a logic gate function, comprising: a first and a second P channel transistor coupled in parallel between a first voltage node and the output, the first P channel transistor having a gate electrode coupled to the first input and the second P channel transistor having a gate electrode coupled to the second input; a first and a second N channel transistor connected in series and coupled to the output, the first N channel transistor having a gate electrode coupled to the first input and the second N channel transistor having a gate electrode coupled to the second input; and a third and a fourth N channel transistor coupled in series between a second voltage node and the first and second N channel transistors, the third N channel transistor having a gate electrode coupled to the first input and the fourth N channel transistor having a gate electrode coupled to the second input, each of the N channel transistors having a separate tub, the tubs of the first and second N channel transistors being connected to the source of the second N channel transistor, the tubs of the third and fourth transistors being coupled to the second voltage node to provide at least two N channel transistors in series in a nonconducting state when the output is at a potential substantially equal to a voltage present at the first voltage node.

Claim 12

A CMOS circuit having high voltage capability and having at least a first and a second input and an output and being capable of performing a logic gate function, comprising: a first and a second P channel transistor coupled in parallel between a first voltage node and the output, the first P channel transistor having a gate electrode coupled to the first input and the second P channel transistor having a gate electrode coupled to the second input; a first and a second N channel transistor connected in series and coupled to the output, the first N channel transistor having a gate electrode coupled to the first input and the second N channel transistor having a gate electrode coupled to the second input; and a third and a fourth N channel transistor coupled in series between a second voltage node and the first and second N channel transistors, the third N channel transistor having a gate electrode coupled to the first input and the fourth N channel transistor having a gate electrode coupled to the second input, each of the N channel transistors having a separate tub, the tubs of the first and second N channel transistors being connected to the source of the second N channel transistor, the tubs of the third and fourth transistors being coupled to the second voltage node to provide at least two N channel transistors in series in a nonconducting state when the output is at a potential substantially equal to a voltage present at the first voltage node.