Patent US5448512A successfully refreshed from Google Patents.
US5448512A
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Semiconductor memory device with contact region intermediate memory cell and peripheral circuit
Assignee: Renesas Electronics Corp
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Filing: 1993-04-09
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Granted: 1995-09-05
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Expires: 2013-04-09
Abstract
Abstract A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.
Inventors
- 👤 Atsushi Hachisuka
- 👤 Kazuhiro Tsukamoto
- 👤 Mitsuya Kinoshita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:47
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
230 words
A semiconductor memory device comprising: a memory cell formation region in which a memory cell is formed on a semiconductor substrate having a main surface, an impurity region formed on said main surface, a storage node having a node surface and formed to be electrically connected to said impurity region and having a portion extending upwards with respect to said main surface, a dielectric film having a dielectric surface and formed on the node surface of said storage node, a cell plate formed on the dielectric surface of said dielectric film, a first interlayer insulating film having an upper face portion and formed on said main surface substantially laterally spaced from said memory cell formation region, a lower interconnection layer formed substantially laterally between said memory cell formation region and said first interlayer insulating film, and said lower interconnection layer comprising a portion of said cell plate, a second interlayer insulating film formed substantially laterally between said memory cell formation region and said first interlayer insulating film, and having a through hole exposing said lower interconnection layer, and an upper interconnection layer formed on said second interlayer insulating film, and electrically connected to said lower interconnection layer via said through hole, wherein said lower and upper interconnection layers and said second interlayer insulating film are positioned substantially laterally between said memory cell formation region and said first interlayer insulating film.
Claim 2
Dependent Claim
230 words
A semiconductor memory device comprising: a memory cell formation region in which a memory cell is formed on a semiconductor substrate having a main surface, an impurity region formed on said main surface, a storage node having a node surface and formed to be electrically connected to said impurity region and having a portion extending upwards with respect to said main surface, a dielectric film having a dielectric surface and formed on the node surface of said storage node, a cell plate formed on the dielectric surface of said dielectric film, a first interlayer insulating film having an upper face portion and formed on said main surface substantially laterally spaced from said memory cell formation region, a lower interconnection layer formed substantially laterally between said memory cell formation region and said first interlayer insulating film, and said lower interconnection layer comprising a portion of said cell plate, a second interlayer insulating film formed substantially laterally between said memory cell formation region and said first interlayer insulating film, and having a through hole exposing said lower interconnection layer, and an upper interconnection layer formed on said second interlayer insulating film, and electrically connected to said lower interconnection layer via said through hole, wherein said lower and upper interconnection layers and said second interlayer insulating film are positioned substantially laterally between said memory cell formation region and said first interlayer insulating film.
Claim 3
Dependent Claim
33 words
The semiconductor memory device according to claim 1, wherein said lower interconnection layer has a concave shape, wherein said through hole reaches the bottom of said concave shape of the lower interconnection layer.
Claim 4
Dependent Claim
20 words
The semiconductor memory device according to claim 1, wherein said lower interconnection layer extends upon said first interlayer insulating layer.
Claim 5
Dependent Claim
20 words
The semiconductor memory device according to claim 1, wherein the depth of said through hole is at least 5000 Å.
Claim 6
Dependent Claim
20 words
The semiconductor memory device according to claim 1, wherein an element isolation insulating layer is positioned below said through hole.
Claim 7
Dependent Claim
33 words
The semiconductor memory device according to claim 2, wherein the length of the bottom of said concave shape of the lower interconnection layer is at least 1.0 μm and at most 3.0 μm.
Claim 8
Dependent Claim
169 words
A semiconductor memory device, comprising: a memory cell formation region including a substrate with a main surface, the main surface including first and second main surface portions; an impurity region formed on the first main surface portion; a storage node having wall and base portions, the base portion formed on said impurity region; a dielectric film formed on said storage node; and a cell plate formed on said dielectric film; a first insulating film formed on the second main surface portion substantially laterally spaced from said first main surface; a lower interconnection layer formed substantially laterally between said memory cell formation region and said first insulating film, said lower interconnection layer comprising a portion of said cell plate; a second insulating film formed substantially laterally between said memory cell formation region and said first insulating film, and having a through hole exposing said lower interconnection layer; and an upper interconnection layer formed on said second insulating film, and electrically connected to said lower interconnection layer via said through hole.
Claim 9
Dependent Claim
169 words
A semiconductor memory device, comprising: a memory cell formation region including a substrate with a main surface, the main surface including first and second main surface portions; an impurity region formed on the first main surface portion; a storage node having wall and base portions, the base portion formed on said impurity region; a dielectric film formed on said storage node; and a cell plate formed on said dielectric film; a first insulating film formed on the second main surface portion substantially laterally spaced from said first main surface; a lower interconnection layer formed substantially laterally between said memory cell formation region and said first insulating film, said lower interconnection layer comprising a portion of said cell plate; a second insulating film formed substantially laterally between said memory cell formation region and said first insulating film, and having a through hole exposing said lower interconnection layer; and an upper interconnection layer formed on said second insulating film, and electrically connected to said lower interconnection layer via said through hole.
Claim 10
Dependent Claim
33 words
The semiconductor memory device according to claim 7, wherein said lower and upper interconnection layers and said second insulating film are positioned between said memory cell formation region and said first insulating film.
Claim 11
Dependent Claim
26 words
The semiconductor memory device according to claim 7, wherein said dielectric layer prevents substantial conductance of electricity between said upper interconnection layer and said impurity region.
Claim 12
Dependent Claim
23 words
The semiconductor memory device according to claim 7, wherein said dielectric layer is interposed between said upper interconnection layer and said impurity region.
Claim 13
Dependent Claim
23 words
The semiconductor memory device according to claim 7, wherein said lower interconnection layer covers a plurality of memory cells disposed on the substrate.
Claim 14
Dependent Claim
25 words
The semiconductor memory device according to claim 7, wherein said lower interconnection layer is continuous over a plurality of memory cells disposed on the substrate.
Claim 15
Dependent Claim
25 words
The semiconductor memory device according to claim 7, wherein the through hole in said lower interconnection layer is formed outside the memory cell formation region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |