Antifuse programming method and circuit which supplies a steady current after a programming voltage has dropped

Claim 2

An integrated circuit, supplied with a supply voltage Vcc, said integrated circuit comprising: an antifuse including terminals; and a programming circuit for programming the antifuse, the programming circuit using a programming voltage Vpp that is substantially higher than the supply voltage Vcc, wherein the programming circuit comprises means to apply the supply voltage Vcc to the terminals of the antifuse immediately after an application of the programming voltage Vpp to the terminals of the antifuse so that programming of the antifuse is not interrupted.

Claim 3

An integrated circuit according to claim 1, further comprising a source of programming voltage Vpp that is a source internal to the integrated circuit, said source of programming voltage Vpp producing the programming voltage Vpp from the supply voltage Vcc.

Claim 4

An integrated circuit according to claim 1, further comprising a first transistor connected between a source of programming voltage Vpp and the antifuse, and a second transistor connected between a source of supply voltage Vcc and the antifuse.

Claim 5

An integrated circuit according to claim 3, further comprising an insulation transistor, wherein a gate of the first transistor is controlled, through the insulation transistor, by a programming command signal FB, and a gate of the second transistor is controlled by the programming command signal FB.

Claim 6

An integrated circuit according to claim 4, wherein the insulation transistor includes a gate that is controlled by the supply voltage Vcc and the means to apply the supply voltage Vcc to the terminals of the antifuse applies the supply voltage Vcc to the terminals of the antifuse when a resistance of the antifuse is at a lowest level.

Claim 7

An integrated circuit according to claim 4, wherein a drain of the first transistor is connected to a gate of the first transistor through a bias transistor mounted as a resistive means.

Claim 8

An integrated circuit according to claim 1, further comprising a first transistor connected between a source of programming voltage Vpp and the antifuse, a second transistor connected between a source of supply voltage Vcc and the source of programming voltage Vpp and a third transistor also connected between the source of supply voltage Vcc and the source of programming voltage Vpp, wherein the second transistor is controlled by a programming command signal FB through an insulation transistor having a gate that is controlled by the programming voltage Vpp, and the third transistor is controlled directly by the programming command signal FB.

Claim 9

An integrated circuit according to claim 1, wherein the antifuse includes two conductors separated by an insulator that is capable of breaking down under the effect of an electrical field generated in the insulator by the application of the programming voltage Vpp between the two conductors just before the supply voltage Vcc is applied to the terminals of the antifuse.

Claim 10

An integrated circuit according to claim 7, further comprising a current limiting transistor interposed between one end of the antifuse and a ground.

Claim 11

An integrated circuit according to claim 9, further comprising a bootstrap structure having i) a first end connected to the antifuse and being capable of being charged by the programming voltage Vpp during the application of the programming voltage Vpp to the antifuse and ii) a second end receiving a signal BOOST that includes a voltage square-wave signal that starts when the programming voltage Vpp has reached substantially a nominal value.

Claim 14

A method according to claim 11, wherein the voltage supply source provides a current of at least two milliamperes for at least twenty milliseconds to the antifuse when a resistance of the antifuse is at a lowest level.

Claim 15

A method according to claim 11, wherein said antifuse includes a layer of insulator between two conductors and programming said antifuse includes converting said layer of insulator into a resistive layer just before the antifuse is connected to the voltage supply source.

Claim 16

A method according to claim 12, wherein said antifuse includes a layer of insulator between two conductors and programming said antifuse includes converting said layer of insulator into a resistive layer just before the antifuse is connected to the voltage supply source.

Claim 17

An integrated circuit, supplied with a supply voltage Vcc, the integrated circuit comprising: an antifuse including terminals; and a programming circuit that uses a programming voltage Vpp that is substantially higher than the supply voltage Vcc, said programming circuit including a first transistor, a first end of said first transistor being connected to a source of programming voltage Vpp, a second end of said first transistor being connected to the antifuse, and a gate of said first transistor being controlled by a programming command signal FB; a second transistor, a first end of said second transistor being connected to a source of supply voltage Vcc, a second end of said second transistor being connected to the source of programming voltage Vpp, and a gate of said second transistor being controlled by the programming command signal FB; a third transistor, a first end of said third transistor being connected to the source of supply voltage Vcc, a second end of said third transistor being connected to the source of programming voltage Vpp, and a gate of said third transistor being controlled by the programming command signal FB; and an insulation transistor, a first end of said insulation transistor being connected to a source of programming command signal FB, and a second end of said insulation transistor being connected to the gate of the first transistor, wherein the supply voltage Vcc can be applied to the terminals of the antifuse immediately after an application of the programming voltage Vpp to the terminals of the antifuse so that the programming of the antifuse is not interrupted.

Claim 18

An integrated circuit, supplied with a supply voltage Vcc, the integrated circuit comprising: an antifuse including terminals; and a programming circuit that uses a programming voltage Vpp that is substantially higher than the supply voltage Vcc, said programming circuit including a first transistor, a first end of said first transistor being connected to a source of programming voltage Vpp, a second end of said first transistor being connected to the antifuse, and a gate of said first transistor being controlled by a programming command signal FB; a second transistor, a first end of said second transistor being connected to a source of supply voltage Vcc, a second end of said second transistor being connected to the source of programming voltage Vpp, and a gate of said second transistor being controlled by the programming command signal FB; a third transistor, a first end of said third transistor being connected to the source of supply voltage Vcc, a second end of said third transistor being connected to the source of programming voltage Vpp, and a gate of said third transistor being controlled by the programming command signal FB; and an insulation transistor, a first end of said insulation transistor being connected to a source of programming command signal FB, and a second end of said insulation transistor being connected to the gate of the first transistor, wherein the supply voltage Vcc can be applied to the terminals of the antifuse immediately after an application of the programming voltage Vpp to the terminals of the antifuse so that the programming of the antifuse is not interrupted.

Claim 19

An integrated circuit according to claim 15, wherein the insulation transistor includes a gate that is controlled by the supply voltage Vcc and the supply voltage Vcc is applied to the terminals of the antifuse when a resistance of the antifuse is at a lowest level.

Claim 20

An integrated circuit according to claim 15, wherein said first end of said first transistor is a drain, said second end of said first transistor is a source and said drain of said first transistor is connected to said gate of said first transistor through a bias transistor mounted as a diode.

Claim 21

An integrated circuit according to claim 10, further comprising an insulation transistor, wherein the gate of the first transistor is controlled, through the insulation transistor, by the programming command signal FB.

Claim 22

An integrated circuit according to claim 18, wherein the insulation transistor includes a gate that is controlled by the supply voltage Vcc and the means to apply supply voltage Vcc to the terminals of the antifuse applies the supply voltage Vcc to the terminals of the antifuse when a resistance of the antifuse is at a lowest level.

Claim 23

An integrated circuit according to claim 18, wherein the drain of the first transistor is connected to the gate of the first transistor through a bias transistor mounted as a resistive means.