Field-programmable gate array

Claim 2

A field-programmable gate array comprising: regularly arrayed logic elements; a first group of signal lines regularly disposed and each interconnecting only one logic element and another logic element adjacent to the one logic element; and a second group of signal lines regularly disposed and each interconnecting only one logic element and another logic element not adjacent to the one logic element.

Claim 3

A field-programmable gate array according to claim 1, wherein each of the logic elements has a logic circuit for outputting signals to the logic elements not adjacent thereto.

Claim 4

A field-programmable gate array according to claim 2, wherein the logic circuit for outputting signals outputs signals corresponding to input signals received through the first and the second groups of signal lines.

Claim 5

A field-programmable gate array comprising: a first logic element; a plurality of second logic elements adjacent to the first logic element; and a plurality of third logic elements adjacent to the second logic elements; each logic element having: an input selector for selecting a predetermined number of input signals from a plurality of input signals; logic circuit performing a logic function on the predetermined number of input signals; a plurality of signal output means coupled to the logic circuit, each outputting a signal in response to the predetermined number of input signals; selection and output means for selecting a signal outputted from one of the plurality of signal output means and outputting the selected signal; a plurality of first output selectors, each being connected to one of the plurality of signal output means and the selection and output means; a plurality of second output selectors, each being connected to all the plurality of signal output means and the selection and output means; and control means for controlling each input and first and second output selectors and the selection and output means; wherein the first output selector of the first logic element is connected to the input selector of each second logic element, and the second output selector of the first logic element is connected to the input selector of each third logic element.

Claim 6

A field-programmable gate array comprising: a first logic element; a plurality of second logic elements adjacent to the first logic element; and a plurality of third logic elements adjacent to the second logic elements; each logic element having: an input selector for selecting a predetermined number of input signals from a plurality of input signals; logic circuit performing a logic function on the predetermined number of input signals; a plurality of signal output means coupled to the logic circuit, each outputting a signal in response to the predetermined number of input signals; selection and output means for selecting a signal outputted from one of the plurality of signal output means and outputting the selected signal; a plurality of first output selectors, each being connected to one of the plurality of signal output means and the selection and output means; a plurality of second output selectors, each being connected to all the plurality of signal output means and the selection and output means; and control means for controlling each input and first and second output selectors and the selection and output means; wherein the first output selector of the first logic element is connected to the input selector of each second logic element, and the second output selector of the first logic element is connected to the input selector of each third logic element.

Claim 7

A field-programmable gate array according to claim 4, wherein each of the logic elements has four signal output means, four first output selectors, and four second output selectors.

Claim 8

A field-programmable gate array according to claim 4, wherein each of the logic elements has four signal output means, four first output selectors, and two second output selectors.

Claim 9

A field-programmable gate array according to claim 4, wherein the logic elements, each being rectangular, are juxtaposed in the form of a cross.

Claim 10

A field-programmable gate array according to claim 4, wherein the first, second, and third logic elements are disposed in a diagonal arrangement.

Claim 11

A field-programmable gate array according to claim 4, wherein latching means latches the received signal by the control of a clock input signal and an input enable signal.

Claim 12

A field-programmable gate array according to claim 4, further comprising latching means connected to the selection and output means for receiving one of the signals outputted from the selection and output means, the latching means latching the one signal.