US5446959A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of packaging a power semiconductor device
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1994-07-06
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Granted: 1995-09-05
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Expires: 2014-07-06
Abstract
Abstract A method of packaging a power semiconductor device is disclosed, comprising the steps of preparing a lead frame including a paddle for providing a semiconductor chip on a top surface thereof, tie bars for supporting said paddle, wherein said paddle being provided lower in horizontal surface than the leads; attaching a heat radiating plate on a bottom surface of the paddle by cladding; attaching a Kovar plate on the top surface of the paddle by soldering, said Kovar plate having similar heat expansion coefficient to that of the chip; providing the chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polyimide over the semiconductor chip by spin-coating; curing the polyimide coated thus; forming a metal cap above the said paddle by soldering, and injecting a molding material into a molder for enclosing the paddle and curing the molding material injected thus the method can be applied to produce a plastic package of a power semiconductor device at low cost. The metal cap is grounded through the tie bars as a source electrode to shield a noise.
Inventors
- 👤 Dong-Goo Kim
- 👤 Min-Kyu Song
- 👤 Seong-Su Park
- 👤 Seung-Goo Kang
- 👤 Hyung-Jin Yoon
- 👤 Hyung-Moo Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:30
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/10; H10W40/70; H10W40/77; H10W40/778; H10W42/00; H10W42/60; H10W44/00; H10W44/20; H10W70/00; H10W70/01; H10W70/02; H10W70/04; H10W70/40; H10W70/411; H10W70/417; H10W70/481; H10W72/00; H10W72/50; H10W74/00; H10W74/01; H10W74/016; H10W76/00; H10W76/10; H10W76/12; H10W76/17; H10W76/18; H10W76/60; H10W90/00; H10W90/811; H10W72/071; H10W72/073; H10W72/075; H10W72/07551; H10W72/07554; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/381; H10W72/541; H10W72/5445; H10W72/547; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; H10W99/00; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
190 words
A method of packaging a power semiconductor device, the method comprising the steps of: preparing a lead frame including a support base for providing a semiconductor chip on a top surface thereof, a gate electrode lead, a drain electrode lead and tie bars for supporting said support base, wherein said support base being provided lower in horizontal surface than the gate electrode lead or the drain electrode lead; attaching a heat radiating plate on a bottom surface of the support base by cladding; attaching a Kovar plate on the top surface of the support base by soldering, said Kovar plate having similar heat expansion coefficient to that of the semiconductor chip, so as to remove a stress caused due to a difference in heat expansion coefficient between the chip and the lead frame; providing the semiconductor chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polymide over the semiconductor chip by spin-coating; curing the polymide coated thus; injecting a molding material into a molder for enclosing the support base and curing the molding material injected thus.
Claim 2
Independent Claim
190 words
A method of packaging a power semiconductor device, the method comprising the steps of: preparing a lead frame including a support base for providing a semiconductor chip on a top surface thereof, a gate electrode lead, a drain electrode lead and tie bars for supporting said support base, wherein said support base being provided lower in horizontal surface than the gate electrode lead or the drain electrode lead; attaching a heat radiating plate on a bottom surface of the support base by cladding; attaching a Kovar plate on the top surface of the support base by soldering, said Kovar plate having similar heat expansion coefficient to that of the semiconductor chip, so as to remove a stress caused due to a difference in heat expansion coefficient between the chip and the lead frame; providing the semiconductor chip on the Kovar plate by soldering; wire-bonding terminals of said semiconductor chip to the corresponding leads of the lead frame, respectively; coating polymide over the semiconductor chip by spin-coating; curing the polymide coated thus; injecting a molding material into a molder for enclosing the support base and curing the molding material injected thus.
Claim 3
Dependent Claim
39 words
The method according to claim 1, wherein the step of attaching said Kovar plate is performed using an alloy including Pb, In and Ag in the ratio of 92.5:5:2.5 in the range of 290° to 310° C. in temperature.
Claim 4
Dependent Claim
40 words
The method according to claim 1, wherein the step of coating and curing said polyimide is performed in a spin speed of 3000 rpm and at a curing temperature of 220° C. so as to have thickness of 5 μm.
Claim 5
Dependent Claim
38 words
The method according to claim 1, wherein the step of forming said metal cap is performed using an alloy including Sn and Sb in the ratio of 95:5 in the range of 240° to 250° C. in temperature.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |