US5446410A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Panasonic Holdings Corp
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Filing: 1993-04-19
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Granted: 1995-08-29
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Expires: 2013-04-19
Abstract
Abstract Provided on the periphery of a semiconductor chip are a clock input pad 10 and a clock driver 11. Clock pulse generators 13A to 13G are provided to functional blocks 12A to 12F. A clock signal line 14, through which clock signals are transmitted to the clock pulse generators 13A to 13G, is composed of a first clock line 14a extending from the clock driver 14 to the center of the semiconductor chip, and a plurality of second clock lines branching, at the center of the semiconductor chip, from the leading end of the first clock line to extend to the clock pulse generators 13A to 13G respectively.
Inventors
- 👤 Yasuhiro Nakakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:08
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
95 words
A semiconductor integrated circuit comprising a plurality of functional blocks provided on a semiconductor chip and a multi-level metal interconnect-wiring layer, wherein: particular one of said plurality of metal interconnect-wiring layers is for the exclusive use of a power supply line which delivers power to said plurality of functional blocks and a clock signal line through which a clock signal is transmitted to said plurality of functional blocks, and the minimum width of the lines on said particular metal interconnect-wiring layer is greater than the maximum width of lines on the remaining metal interconnect-wiring layers.
Claim 2
Dependent Claim
95 words
A semiconductor integrated circuit comprising a plurality of functional blocks provided on a semiconductor chip and a multi-level metal interconnect-wiring layer, wherein: particular one of said plurality of metal interconnect-wiring layers is for the exclusive use of a power supply line which delivers power to said plurality of functional blocks and a clock signal line through which a clock signal is transmitted to said plurality of functional blocks, and the minimum width of the lines on said particular metal interconnect-wiring layer is greater than the maximum width of lines on the remaining metal interconnect-wiring layers.
Claim 3
Dependent Claim
22 words
A semiconductor integrated circuit as in claim 1, wherein said particular metal interconnect-wiring layer is an uppermost-level layer in the semiconductor chip.
Claim 4
Dependent Claim
30 words
A semiconductor integrated circuit as in claim 2, wherein said particular metal interconnect-wiring layer is provided with no interconnect-wirings except for said power supply line and said clock signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |