US5148263A
Expired / Lapsed
US
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Semiconductor device having a multi-layer interconnect structure
Assignee: Toshiba Corp
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Filing: 1991-04-12
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Granted: 1992-09-15
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Expires: 2011-04-12
Abstract
Abstract A semiconductor device has a multi-layer structure comprising three or more interconnect layers formed over a substrate, one of these interconnect layers being a first power supply line and another metal interconnect layer being a second power supply line, the first and second power supply lines being arranged in a multi-level fashion such that one is superposed relative to the other in a plan view. That is, the power supply lines are arranged as a multi-layer metal interconnect layer array such that the first and second power supply lines are superposed in a multi-level fashion in a plan view.
Inventors
- 👤 Tsuneo Hamai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:54
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/038; H10W20/40; H10W20/41; H10W20/427; H10W20/046; H10W20/495
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
86 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line, wherein said first power supply line comprises a plurality of interconnect layers; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line. the first and second power supply lines each being a closed trunk line for applying voltages to said device.
Claim 2
Dependent Claim
86 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line, wherein said first power supply line comprises a plurality of interconnect layers; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line. the first and second power supply lines each being a closed trunk line for applying voltages to said device.
Claim 3
Dependent Claim
86 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line, wherein said second power supply line comprises a plurality of interconnect layers, the first and second power supply lines each being a closed trunk line for applying voltages to said device.
Claim 4
Dependent Claim
86 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line, wherein said second power supply line comprises a plurality of interconnect layers, the first and second power supply lines each being a closed trunk line for applying voltages to said device.
Claim 5
Dependent Claim
90 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line, the first and second power supply lines each being a closed trunk line for applying voltages to said device, and wherein said first and second power supply lines each comprise a plurality of interconnect layers.
Claim 6
Dependent Claim
90 words
A semiconductor device having a multi-layer metal interconnect structure comprising: at least three metal interconnect layers formed over a substrate; a first metal interconnect layer constituting a first power supply line; and a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line, the first and second power supply lines each being a closed trunk line for applying voltages to said device, and wherein said first and second power supply lines each comprise a plurality of interconnect layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |