Semiconductor device

Claim 2

A field effect transistor in which a current flowing between a drain region and a source region is controlled by a voltage applied to a gate electrode, said field effect transistor comprising: a buffer layer; and a channel region formed on said buffer layer and made up of a multi-layer structure, said multi-layer structure including a lower electron supply layer consisting of a first compound semiconductor which is formed of a material different from that of said buffer layer, said lower electron supply layer being formed directly on said buffer layer; a channel formation semiconductor layer consisting of an undoped second compound semiconductor formed directly on said lower electron supply layer; and an upper electron supply layer consisting of said first compound semiconductor formed directly on said channel formation semiconductor layer; whereby when a voltage is supplied to said gate electrode, channels are formed in said channel formation semiconductor layer, and electrons for said channel formation semiconductor layer are furnished by real space transition flow through said lower and said upper electron supply layers.

Claim 3

A field effect transistor according to claim 1, further comprising: a first semiconductor layer contacting said upper electron supply layer of said channel region and forming a potential barrier in an interface with said upper electron supply layer; and a second semiconductor layer contacting said lower electron supply layer of said channel region and forming a potential barrier in an interface with said lower electron supply layer.

Claim 4

A field effect transistor according to claim 2, wherein said channel region is formed over a semi-insulating semiconductor substrate consisting of a third compound semiconductor.

Claim 5

A field effect transistor according to claim 3, wherein said first semiconductor layer has a planar structure at a part thereof which is directly in contact with said gate electrode.

Claim 6

A field effect transistor according to claim 2, wherein said first compound semiconductor includes a compound semiconductor doped with a n-typed impurity, and said first compound semiconductor has a sufficient electron saturation rate such that mobility is equivalent to that of a two-dimensional electron gas formed in said channel formation semiconductor layer.

Claim 7

A field effect transistor according to claim 5, wherein when a voltage is supplied to said gate electrode, a first channel is a two,dimensional electron gas formed in an upper region of said channel formation semiconductor layer, and a second channel is a two-dimensional electron gas formed in a lower region of said channel formation semiconductor layer; said first channel being supplied electrons from said upper electron supply layer, and said second channel being supplied electrons from said lower electron supply layer.

Claim 8

A field effect transistor according to claim 2, wherein each of said lower and upper electron supply layers has a thickness sufficient to allow electron flow therein; and said electrons from said channel formation semiconductor layer being created by the real space transition.

Claim 9

A field effect transistor according to claim 7, wherein said upper electron supply layer has an electron supply density sufficient to form a Schottky junction with said gate electrode.

Claim 10

A field effect transistor in which a current flowing between a drain region and a source region is controlled by a voltage applied to a gate electrode, said field effect transistor comprising: an AlInAs buffer layer; and a channel region formed on said buffer layer and made up of a multi-layer structure, said multi-layer structure including a lower InP layer formed directly on said buffer layer, an undoped InGaAs layer formed directly on said lower InP layer, and an upper InP layer formed directly on said undoped InGaAs layer, said undoped InGaAs layer being sandwiched between said lower and upper InP layers.

Claim 11

A field effect transistor in which a current flowing between a drain region and a source region is controlled by a voltage applied to a gate electrode, said field effect transistor comprising: an AlInAs buffer layer; and a channel region formed on said buffer layer and made up of a multi-layer structure, said multi-layer structure including a lower InP layer formed directly on said buffer layer, an undoped InGaAs layer formed directly on said lower InP layer, and an upper InP layer formed directly on said undoped InGaAs layer, said undoped InGaAs layer being sandwiched between said lower and upper InP layers.

Claim 12

A field effect transistor according to claim 9, further comprising: a first semiconductor layer contacting said upper InP layer of said channel region and forming a potential barrier at an interface with said upper InP layer; and a second semiconductor layer contacting said lower InP layer of said channel region and forming a potential barrier at an interface with said lower InP layer.

Claim 13

A field effect transistor according to claim 10, wherein said channel region is formed over a semi-insulating InP substrate.

Claim 14

A field effect transistor according to claim 11, wherein said first semiconductor layer has a planar structure at a part thereof which is in direct contact with said gate electrode.

Claim 15

A field effect transistor according to claim 9, wherein each of said lower and upper InP layers includes a n-type InP.

Claim 16

A field effect transistor according to claim 13, wherein when a voltage is supplied to said gate electrode, a first channel is a two-dimensional electron gas formed in an upper region of said undoped InGaAs layer, and a second channel is a two-dimensional electron gas formed in a lower region of said undoped InGaAs layer; said first channel is supplied electrons from said upper InP layer, and said second channel is supplied electrons from said lower InP layer.

Claim 17

A field effect transistor according to claim 10, wherein said first semiconductor layer includes AlInAs.

Claim 18

A field effect transistor according to claim 13, wherein said undoped InGaAs layer has a thickness of 5 to 15 nm.

Claim 19

A field effect transistor according to claim 13, wherein each of said lower and upper InP layers has a thickness of 10 to 50 nm.

Claim 20

A field effect transistor according to claim 12, wherein said first semiconductor layer has a thickness of 10 to 30 nm.

Claim 21

A field effect transistor according to claim 9, wherein said second semiconductor layer has a thickness of 100 to 600 nm.

Claim 22

A field effect transistor according to claim 9, wherein said upper InP layer has a thickness sufficient for electrons to flow therein; said electrons from said undoped InGaAs layer occurring due to real space transition.

Claim 23

A field effect transistor according to claim 9, wherein said upper InP layer has an electron density sufficient to form a Schottky junction with said gate electrode.

Claim 24

A field effect transistor in which a current flowing between a drain region and a source region is controlled by a voltage applied to a gate electrode, said field effect transistor comprising: a buffer layer; and a channel region formed on said buffer layer and made up of a multi-layer structure, said multi-layer structure including: a lower electron supply layer consisting of a first compound semiconductor which is formed of a material different than that of said buffer layer, said lower electron supply layer being formed directly on said buffer layer; a channel formation semiconductor layer consisting of an undoped second compound semiconductor formed directly on said lower electron supply layer; and an upper electron supply layer consisting of said first compound semiconductor formed directly on said channel formation semiconductor layer, said channel formation semiconductor layer being sandwiched between said lower and upper electron supply layers, whereby said first compound semiconductor has a sufficient electron saturation rate such that said first compound semiconductor has a mobility equivalent to that of a two-dimensional electron gas formed in said channel formation semiconductor layer.

Claim 25

A field effect transistor in which a current flowing between a drain region and a source region is controlled by a voltage applied to a gate electrode, said field effect transistor comprising: a buffer layer; and a channel region formed on said buffer layer and made up of a multi-layer structure, said multi-layer structure including: a lower electron supply layer consisting of a first compound semiconductor which is formed of a material different than that of said buffer layer, said lower electron supply layer being formed directly on said buffer layer; a channel formation semiconductor layer consisting of an undoped second compound semiconductor formed directly on said lower electron supply layer; and an upper electron supply layer consisting of said first compound semiconductor formed directly on said channel formation semiconductor layer, said channel formation semiconductor layer being sandwiched between said lower and upper electron supply layers, whereby said first compound semiconductor has a sufficient electron saturation rate such that said first compound semiconductor has a mobility equivalent to that of a two-dimensional electron gas formed in said channel formation semiconductor layer.

Claim 26

A field effect transistor according to claim 22, further comprising: a first semiconductor layer formed on and contacting said upper electron supply layer of said channel region and forming a potential barrier at an interface with said upper electron supply layer; and a second semiconductor layer formed on and contacting said lower electron supply layer of said channel region and forming a potential barrier at an interface with said lower electron supply layer.

Claim 27

A field effect transistor according to claim 23, wherein said channel region is formed over a semi-insulating semiconductor substrate consisting of a third compound semiconductor.

Claim 28

A field effect transistor according to claim 23, wherein said first semiconductor layer has a planar structure at a part thereof which is in direct contact with said gate electrode.

Claim 29

A field effect transistor according to claim 22, wherein said first compound semiconductor includes a compound semiconductor doped with an n-type impurity.

Claim 30

A field effect transistor according to claim 22, wherein when a voltage is supplied to said gate electrode, a first channel comprises a two-dimensional electron gas formed in an upper region of said channel formation semiconductor layer, and a second channel comprises a two-dimensional electron gas formed in a lower region of said channel formation semiconductor layer; said first channel being supplied electrons from said upper electron supply layer, and said second channel being supplied electrons from said lower electron supply layer.

Claim 31

A field effect transistor according to claim 27, wherein each of said lower and upper electron supply layers has a thickness sufficient to allow electron flow therein; and said electrons from said channel formation semiconductor layer being created by real space transition.

Claim 32

A field effect transistor according to claim 28, wherein said upper semiconductor layer has an electron density sufficient to create a Schottky junction with said gate electrode.