Patterning method

Claim 1

A patterning method for manufacturing a field effect transistor to form an etching pattern on a ceramic insulating substrate comprising the steps of: forming a conductive metal layer and a first p-type silicon layer on the ceramic insulating substrate in this order; forming an n-type silicon layer on the first p-type silicon layer; forming a second p-type silicon layer on the n-type silicon layer; forming a photosensitive inorganic semiconductor layer on the second p-type silicon layer; irradiating a portion of the photosensitive inorganic semiconductor layer, which is kept in contact with an electrolyte, with light having energy greater than the band gap of the photosensitive inorganic semiconductor layer thereby causing the light-irradiated portion of the photosensitive inorganic semiconductor layer to dissolve into the electrolyte by optoelectrochemical reaction, to form a pattern; forming a source electrode and a drain electrode, both being made of conductive metal, on the n-type silicon layer using said pattern, the second p-type silicon layer being interposed between the source electrode and the drain electrode; removing a remaining portion of the photosensitive inorganic semiconductor layer with an alkaline cleaning solution; and disposing a gate electrode made of conductive metal on the second p-type silicon layer, wherein the photosensitive inorganic semiconductor layer is selected from the group consisting of tungsten oxide and zinc oxide.