Patent US5440755A successfully refreshed from Google Patents.
US5440755A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system with a processor-direct universal bus connector and interchangeable bus translator
Assignee: Accelerated Systems Inc
•
Filing: 1992-04-06
•
Granted: 1995-08-08
•
Expires: 2012-04-06
Abstract
Abstract A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration. The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure. The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus. Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus. This unique combination of a motherboard having a universal processor-direct bus with plug in local bus translator cards provides a unique, low cost, flexible solution to the problem of standard and local bus obsolescence, local bus non-upgradeability and local bus non-flexibility.
Inventors
- 👤 John J. Harwer
- 👤 Jimmy D'Jen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:39
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/409
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
224 words
A computer comprising: a microprocessor subsystem module, wherein said microprocessor subsystem module further comprises: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data address signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section coupled to said central processor unit; and a microprocessor subsystem module processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem module via said microprocessor subsystem module processor direct multi-line connector, wherein said bus translator subsystem further comprises: a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem module processor direct multi-line connector for communicating with said microprocessor subsystem module through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector.
Claim 2
Dependent Claim
224 words
A computer comprising: a microprocessor subsystem module, wherein said microprocessor subsystem module further comprises: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data address signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section coupled to said central processor unit; and a microprocessor subsystem module processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem module via said microprocessor subsystem module processor direct multi-line connector, wherein said bus translator subsystem further comprises: a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem module processor direct multi-line connector for communicating with said microprocessor subsystem module through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector.
Claim 3
Dependent Claim
33 words
A computer system as defined in claim 1 further comprising a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol.
Claim 4
Dependent Claim
30 words
A computer system as defined in claim 1 wherein said first expansion bus protocol further comprises any one of a VESA local bus protocol or INTEL PCI local bus protocol.
Claim 5
Dependent Claim
39 words
A computer system as defined in claim 2 wherein said second predetermined expansion bus protocol further comprises any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 6
Dependent Claim
207 words
A computer system comprising: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, cpu data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol, said first expansion bus protocol further comprising any one of a VESA local bus protocol or INTEL PCI local bus protocol; a memory section coupled to said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit protocol independent superset of processor-direct signal lines; and a bus translator, said bus translator comprising: a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector.
Claim 7
Dependent Claim
207 words
A computer system comprising: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit protocol independent superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, cpu data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol, said first expansion bus protocol further comprising any one of a VESA local bus protocol or INTEL PCI local bus protocol; a memory section coupled to said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit protocol independent superset of processor-direct signal lines; and a bus translator, said bus translator comprising: a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit protocol independent superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector.
Claim 8
Dependent Claim
33 words
A computer system as defined in claim 5 further comprising a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol.
Claim 9
Dependent Claim
39 words
A computer system as defined in claim 6 wherein said second predetermined expansion bus protocol further comprises any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 10
Dependent Claim
259 words
A computer system comprising: a microprocessor subsystem, wherein said microprocessor subsystem further comprises: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; and a microprocessor subsystem processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem via said microprocessor subsystem processor direct multi-line connector, wherein said bus translator subsystem further comprises: a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem processor direct multi-line connector for communicating with said microprocessor subsystem through said central processor unit superset of processor-direct signal lines; a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector; a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 11
Dependent Claim
259 words
A computer system comprising: a microprocessor subsystem, wherein said microprocessor subsystem further comprises: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; and a microprocessor subsystem processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; and a bus translator subsystem adapted for electrical connection to said microprocessor subsystem via said microprocessor subsystem processor direct multi-line connector, wherein said bus translator subsystem further comprises: a bus translator subsystem processor direct multi-line connector which mates with said microprocessor subsystem processor direct multi-line connector for communicating with said microprocessor subsystem through said central processor unit superset of processor-direct signal lines; a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator subsytem processor direct multi-line connector; a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 12
Dependent Claim
224 words
A computer system comprising: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; a bus translator comprising: a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector; and a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 13
Dependent Claim
224 words
A computer system comprising: a central processor unit (cpu) having cpu address signal lines, cpu data signal lines and cpu control signal lines which form a central processor unit superset of processor-direct signal lines wherein a subset of said superset of processor-direct signal lines includes cpu address signal lines, CPU data signal lines and cpu control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a memory section in communication with said central processor unit; a cpu processor direct multi-line connector which is in direct electrical communication with said central processor unit superset of processor-direct signal lines; a bus translator comprising: a bus translator processor direct multi-line connector which mates with said cpu processor direct multi-line connector for communicating with said central processor unit through said central processor unit superset of processor-direct signal lines; and a first expansion bus which communicates with said central processor unit and said memory section according to said first expansion bus protocol via said bus translator processor direct multi-line connector; and a second expansion bus which communicates with said central processor unit and said memory section according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 14
Dependent Claim
161 words
A bus translator comprising: a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signals includes CPU address signal lines, CPU data signal lines and CPU control lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector wherein said first expansion bus protocol comprises any one of a VESA local bus protocol or INTEL PCI local bus protocol; and a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus.
Claim 15
Dependent Claim
161 words
A bus translator comprising: a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signals includes CPU address signal lines, CPU data signal lines and CPU control lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector wherein said first expansion bus protocol comprises any one of a VESA local bus protocol or INTEL PCI local bus protocol; and a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus.
Claim 16
Dependent Claim
39 words
A bus translator as defined in claim 10 wherein said second predetermined expansion bus protocol further comprises any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 17
Dependent Claim
159 words
A bus translator comprising; a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) superset of processor-direct signal lines wherein said CPU superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector; a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 18
Dependent Claim
159 words
A bus translator comprising; a bus translator processor direct multi-line connector adapted for connection to a central processor unit (CPU) superset of processor-direct signal lines wherein said CPU superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; a first expansion bus which communicates with said central processor unit according to said first expansion bus protocol via said bus translator processor direct multi-line connector; a second expansion bus which communicates with said central processor unit according to a second predetermined expansion bus protocol comprising any one of an ISA bus protocol, EISA bus protocol, MCA bus protocol, PCI bus protocol, C-bus protocol or S-100 bus protocol.
Claim 19
Independent Claim
163 words
A method of changing the expansion bus protocol on a computer comprising: providing a connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; selecting a first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol; and connecting said first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol to a bus translator thereby forming a first expansion bus which functions in accordance with said first expansion bus protocol.
Claim 20
Independent Claim
163 words
A method of changing the expansion bus protocol on a computer comprising: providing a connection to a central processor unit (CPU) protocol independent superset of processor-direct signal lines wherein said CPU protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines such that a subset of said protocol independent superset of processor-direct signal lines includes CPU address signal lines, CPU data signal lines and CPU control signal lines necessary for implementation of any one of a plurality of specific bus protocols including a first expansion bus protocol; selecting a first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol; and connecting said first subset of said protocol independent superset of processor-direct signal lines necessary for implementation of said first expansion bus protocol to a bus translator thereby forming a first expansion bus which functions in accordance with said first expansion bus protocol.
References Cited (Backward Citations)
US3585599A
Cited
US4213177A
Cited
US4420793A
Cited
US4530066A
Cited
US4530069A
Cited
US4647123A
Cited
US4479198A
Cited
US4975903A
Cited
US4683550A
Cited
US4742477A
Cited
US4639863A
Cited
US4954979A
Cited
US4845609A
Cited
US4905182A
Cited
US4931923A
Cited
US4884069A
Cited
US4862400A
Cited
US5025412A
Cited
US5006961A
Cited
US4885482A
Cited
US4971563A
Cited
US5191657A
Cited
US5072185A
Cited
US5227957A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |