Video apparatus employing VRAMs

Claim 2

A video apparatus for providing video data for a display when coupled to a computer which includes a central processing unit comprising: interface means for interfacing with said central processing unit; a pixel data memory having a plurality of video random-access memories each of which includes a storage array and a shift register; addressing means for addressing said video random-access memories coupled between said interface means and said pixel data memory comprising: (a) row address storage means for storing a row address; (b) column address storage means for storing a column address; (c) row counter means for incrementing said row addresses; (d) column counter means for receiving said column addresses; (e) control means for selecting said row counter means when said column counter reaches a predetermined count, said control means resetting said column counter means when said row counter means is incremented; (f) comparator means for comparing the count in said column counter means with a certain count which is less than said predetermined count so as to provide a signal before said shift registers are emptied, said signal causing new address signals to be generated for said video random-access memories; said pixel data memory being accessed by said addressing means to provide video data for said display.

Claim 3

The video apparatus defined by claim 1 including an adder coupled to receive a control input, a base address, an offset and the outputs of said storage means, the output of said adder being coupled to said storage means.

Claim 4

The video apparatus defined by claim 2 wherein the outputs of said row and column address storage means are added to said offset for new scan lines of said display.

Claim 5

The apparatus defined by claim 3 wherein said certain count, is programmable.

Claim 6

A video apparatus for providing video data for a display when coupled to a computer which includes a 68020 central processing unit and a main memory, said computer including a NUBUS which communicates with said central processing unit and said main memory, comprising: interface means for selectively interfacing with each of said NUBUS or said 68020 central processing unit; a pixel data memory having a plurality of video random-access memories each of which includes a storage array and a shift register; addressing means for addressing said video random-access memories coupled between said interface means and said pixel data memory comprising: (a) row address storage means for storing a row address; (b) column address storage means for storing a column address; (c) a row counter coupled to receive said row address; (d) a column counter coupled to receive said column address; (e) control means for causing said row counter to increment when said column counter reaches a predetermined count; (f) comparator means for comparing the count in said column counter with a certain count which is less than said predetermined count so as to provide a signal before the shift registers in said video random-access memories are emptied, said signal causing new address signals to be generated for said video random-access memories: said pixel data memory being accessed by said addressing means to provide video data for said display.

Claim 7

A video apparatus for providing video data for a display when coupled to a computer which includes a 68020 central processing unit and a main memory, said computer including a NUBUS which communicates with said central processing unit and said main memory, comprising: interface means for selectively interfacing with each of said NUBUS or said 68020 central processing unit; a pixel data memory having a plurality of video random-access memories each of which includes a storage array and a shift register; addressing means for addressing said video random-access memories coupled between said interface means and said pixel data memory comprising: (a) row address storage means for storing a row address; (b) column address storage means for storing a column address; (c) a row counter coupled to receive said row address; (d) a column counter coupled to receive said column address; (e) control means for causing said row counter to increment when said column counter reaches a predetermined count; (f) comparator means for comparing the count in said column counter with a certain count which is less than said predetermined count so as to provide a signal before the shift registers in said video random-access memories are emptied, said signal causing new address signals to be generated for said video random-access memories: said pixel data memory being accessed by said addressing means to provide video data for said display.

Claim 8

The apparatus defined by claim 5 wherein said certain count is programmable.

Claim 9

A video apparatus for providing video data for a display when coupled to a computer which includes a central processing unit and a main memory comprising: interface means for interfacing with said central processing unit; a pixel data memory having a plurality of video random-access memories each of which includes a storage array and a shift register; addressing means for addressing said video random-access memories coupled between said interface means and said pixel data memory comprising: (a) an adder for receiving a base address and an offset; (b) row address storage means for storing a row address received from said adder; (c) column address storage means for storing a column address received from said adder, wherein the outputs of said row and column storage means provide an additional input to said adder; (d) a row counter coupled to receive said row address; (e) a column counter coupled to receive said column address, and clocked at the rate data is shifted from the shift register of said video random-access memories; (f) control means for causing said row counter to increment when said column counter reaches a predetermined count, said control means resetting said column counter when said row counter is incremented; (g) comparator means for comparing the count in said column counter with a certain count which is less than said predetermined count so as to provide a signal before the shift registers in said video random-access memories are emptied, said signal causing said new address signals to be generated for said video random-access memories; said pixel data memory being accessed by said addressing means to provide video data for said display.

Claim 10

A video apparatus for providing video data for a display when coupled to a computer which includes a central processing unit and a main memory comprising: interface means for interfacing with said central processing unit; a pixel data memory having a plurality of video random-access memories each of which includes a storage array and a shift register; addressing means for addressing said video random-access memories coupled between said interface means and said pixel data memory comprising: (a) an adder for receiving a base address and an offset; (b) row address storage means for storing a row address received from said adder; (c) column address storage means for storing a column address received from said adder, wherein the outputs of said row and column storage means provide an additional input to said adder; (d) a row counter coupled to receive said row address; (e) a column counter coupled to receive said column address, and clocked at the rate data is shifted from the shift register of said video random-access memories; (f) control means for causing said row counter to increment when said column counter reaches a predetermined count, said control means resetting said column counter when said row counter is incremented; (g) comparator means for comparing the count in said column counter with a certain count which is less than said predetermined count so as to provide a signal before the shift registers in said video random-access memories are emptied, said signal causing said new address signals to be generated for said video random-access memories; said pixel data memory being accessed by said addressing means to provide video data for said display.

Claim 11

The apparatus defined by claim 7 wherein said row and column address storage means receive said base address from said adder for a certain new frame of said display and for subsequent scan lines of said display said adder providing the sum of the addresses stored in said storage means and said offset.

Claim 12

The apparatus defined by claim 8 wherein said offset is a function of the number of bits of pixel data used for each scan line.

Claim 13

The apparatus defined by claim 9 wherein said certain count is programmable.

Claim 14

In a video apparatus for providing video data for a display when said apparatus is coupled to a computer which includes a central processing unit and a main memory, an improvement comprising: a plurality of video random-access memories each of which includes a memory array which is addressed by a row address and a shift register which is addressed by a column address; addressing means for providing said row address and column address for transfer of said video data directly from said memory array to said shift register; detection means for providing a first signal prior to the end of the shifting of the data from said shift registers, said first signal initiating a time sequence for transfer of said video data from said memory arrays directly to said shift registers in said video random-access memories, thereby permitting either a non-integer or integer number of scan lines per row of said memory array, said detection means provides said first signal when said shift register has a certain number of bits of data remaining and said certain number of bit is programmable; and control means for providing second signals to said video random-access memories when said first signal is received from said detection means; said video random-access memories being addressed by said addressing means.

Claim 15

In a video apparatus for providing video data for a display when said apparatus is coupled to a computer which includes a central processing unit and a main memory, an improvement comprising: a plurality of video random-access memories each of which includes a memory array which is addressed by a row address and a shift register which is addressed by a column address; addressing means for providing said row address and column address for transfer of said video data directly from said memory array to said shift register; detection means for providing a first signal prior to the end of the shifting of the data from said shift registers, said first signal initiating a time sequence for transfer of said video data from said memory arrays directly to said shift registers in said video random-access memories, thereby permitting either a non-integer or integer number of scan lines per row of said memory array, said detection means provides said first signal when said shift register has a certain number of bits of data remaining and said certain number of bit is programmable; and control means for providing second signals to said video random-access memories when said first signal is received from said detection means; said video random-access memories being addressed by said addressing means.

Claim 16

The improvement defined by claim 11 wherein said addressing means comprises: (a) row address storage means for storing said row address; (b) column address storage means for storing said column address; (c) a row counter coupled to receive said row address; (d) a column counter coupled to receive said column address; (d) said control means including means for causing said row counter to increment when said column counter reaches a predetermined count; (f) said detection means being coupled to said column counter.