Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

Claim 2

In a multiprocessor system having a plurality of microprocessors, each of said microprocessors having a cache, a memory port, and an input/output unit (IOU), a memory control unit (MCU) in each of said microprocessors comprising: a switch network; a cache interface circuit; means for coupling said cache interface circuit between said cache and said switch network; an I/O interface circuit; means for coupling said I/O interface circuit between said IOU and said switch network; a memory port interface circuit; means for coupling said memory port interface circuit between said memory port and said switch network; switch arbitration means for arbitrating for said switch network; port arbitration means for arbitrating for said memory port; means for transferring to said port arbitration means a request to transfer data between one of said cache and said IOU and said memory port through said switch network and said port interface circuit; means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said cache and said IOU and said memory port.

Claim 3

The MCU according to claim 1, wherein said switch arbitration means for arbitrating for said switch network includes means for providing one of the following arbitration schemes: (a) slave priority in which priority is based on the slave device and priority is always given to the memory ports first and then to said IOU in a round robin fashion; and (b) master priority in which priority is based on the master device and priority is given to said IOU and then to said cache.

Claim 4

The multiprocessor architecture according to claim 2, wherein highest priority is given to an intervention request.

Claim 5

The multiprocessor system according to claim 1, wherein said cache comprises one of a data cache (D-cache) and an instruction cache (I-cache).

Claim 6

The multiprocessor system according to claim 4, further comprising: means for providing a dynamic priority to said request to transfer data as a function of intrinsic priority assigned to each of said IOU, D-cache and I-cache devices and a plurality of factors that can modify the intrinsic priority, including: (a) existence of a row match between a requested address and a previously serviced request, (b) how many times one of said devices has been denied service, and (c) how many times one of said devices has been serviced without interruption.

Claim 7

The multiprocessor system according to claim 5, wherein said means for providing a dynamic priority assigns a D-cache intervention request highest intrinsic priority.

Claim 8

The multiprocessor system according to claim 5, wherein said requests having row matches have higher priority than said intrinsic priority requests.

Claim 9

The multiprocessor system according to claim 5, wherein row match IOU device requests have higher priority than row match D-cache device requests, and said row match D-cache device requests have higher priority than row match I-cache device requests.

Claim 10

The multiprocessor system according to claim 5, wherein said means for providing a dynamic priority assigns both high and normal intrinsic priority to requests from said IOU device, and normal intrinsic priority to requests from said D-cache device and said I-cache device.

Claim 11

The multiprocessor system according to claim 9, wherein said normal intrinsic priority IOU device requests are higher priority than said normal intrinsic priority D-cache device requests, and said normal intrinsic priority D-cache device requests are higher priority than said normal intrinsic priority I-cache device requests.

Claim 12

The multiprocessor system according to claim 10, further comprising: means for decrementing a counter each time said D-cache or said I-cache device is denied service; and means for increasing priority of D-cache and said I-cache device requests above said normal priority IOU device requests to thereby provide denied service priority requests for said D-cache and said I-cache devices once said counter reaches zero.

Claim 13

The multiprocessor system according to claim 11, wherein D-cache denied service priority requests are higher priority than I-cache denied service priority requests.

Claim 14

The multiprocessor system according to claim 11, wherein said counter can be loaded with any value up to a maximum value of 15.

Claim 15

The multiprocessor system according to claim 1, wherein said cache comprises a data cache (D-cache) and an instruction cache (I-cache).

Claim 16

The multiprocessor system according to claim 14, wherein said cache interface circuit comprises: a D-cache interface circuit; and an I-cache interface circuit.

Claim 17

The multiprocessor system according to claim 15, wherein said means for coupling said cache interface circuit between said cache and said switch network further comprises: means for coupling said D-cache interface circuit between said D-cache and said switch network; and means for coupling said I-cache interface circuit between said I-cache and said switch network.

Claim 18

The MCU according to claim 16 wherein said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD) and further comprising: means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including a MAU address bus, an MAU data bus and an MAU control signal bus; means for temporarily storing an address associated with a request to write to said MAU from one of said D-cache and said IOU if said MAU address bus is not then available to receive said address; means for temporarily storing write data from said source of said request to write to said MAU if said MAU data bus is not then available to receive said write data; means for transferring said address associated with said request to write to said MAU from said source of said request to write to said MAU to said switch request bus (SW -- REQ) and said write data associated therewith to said switch write data bus (SW -- WD); means for transferring said address associated with said request to write to said MAU from said switch request bus (SW -- REQ) to said means for temporarily storing said address associated with said request to write to said MAU; means for transferring said write data from said switch write data bus (SW -- WD) to said means for temporarily storing said write data; and means for transferring said address from said means for temporarily storing said address to said MAU address bus and said write data from said means for temporarily storing said write data to said MAU address and write data buses when said MAU address and write data buses are available to receive said address and said write data.

Claim 19

The MCU according to claim 16 wherein said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD) and further comprising: means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; means for temporarily storing an address associated with a read request to read data from said MAU from one of said D-cache, I-cache and IOU if said MAU address bus is not then available to receive said address; means for temporarily storing said read data from said MAU if said switch read data bus (SW -- RD) is not then available to transfer said read data; means for transferring said address associated with said read request from said source of said request to said switch request bus (SW -- REQ) when said switch request bus (SW -- REQ) is available; means for transferring said address associated with said read request from said switch request bus (SW -- REQ) to said means for temporarily storing said address associated with said read request if said MAU address bus is not then available to receive said address; means for transferring said read data from said MAU data bus to said means for temporarily storing said read data when said MAU address bus is available to receive said address and said switch read bus (SW -- RD) is not available to transfer said read data; and means for transferring said read data from said means for temporarily storing said read data to said switch read data bus (SW -- RD) and from said switch read data bus (SW -- RD) to said source of said request when said switch read data bus (SW -- RD) is available to transfer said read data.

Claim 20

The MCU according to claim 16 wherein said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD) and further comprising: means for transferring a request for an I/O data transfer between one of said D-cache and said I-cache and said IOU through said switch network and said I/O interface circuit; means for sending an IOU available signal from said I/O interface circuit to said switch arbitration means when said I/O interface circuit is available to process said request for an I/O data transfer; and means for transferring an address associated with said request for an I/O data transfer to said I/O interface circuit via said switch request bus (SW -- REQ) when said switch network is available to process said request.

Claim 21

The MCU according to claim 16 wherein said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD) and further comprising: means for transferring write data from one of said D-cache and I-cache to said I/O interface circuit via said switch write data bus (SW -- WD) when said request for an I/O data transfer is a write request; and means for transferring read data from said IOU circuit to one of said D-cache and I-cache via said switch read data bus (SW -- RD) when said request for an I/O data transfer is a read request.

Claim 22

The MCU according to claim 16, further comprising: means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus; a test and set bypass circuit, said test and set bypass circuit having a snoop address generator coupled to said MAU address bus for generating snoop addresses corresponding to addresses on said MAU address bus and a content addressable memory (CAM); means responsive to the execution of a predetermined instruction associated with a request to access a shared memory region for storing the address of a semaphore associated with said region in said CAM; means for comparing said snoop addresses with the contents of said CAM on subsequent requests for said semaphore; and means for sending a semaphore failed signal to the source of said request for said semaphore if said semaphore address is still resident in said CAM to thereby save memory bandwidth.

Claim 23

A multiprocessor system capable of supporting multiple processors according to claim 16, wherein said switch arbitration means for arbitrating for said switch network includes means for providing one of the following arbitration schemes: (a) slave priority in which priority is based on the slave device and priority is always given to the memory ports first and then to said IOU in a round robin fashion; and (b) master priority in which priority is based on the master device and priority is first given to said IOU and then to said D- and I-cache.

Claim 24

The multiprocessor system according to claim 22, wherein I-cache requests are given higher priority than IOU and D-cache requests if a prefetch buffer in the processor corresponding to the I-cache request will soon be empty.

Claim 25

The multiprocessor system according to claim 14, further comprising: means for decrementing a counter each time said IOU device is granted use of said memory port; and means for lowering priority of said IOU device requests below said normal priority D-cache and said normal priority I-cache device requests once said counter reaches zero.

Claim 26

The multiprocessor system according to claim 24, further comprising: means for clearing said counter to a predetermined value when said IOU device is not granted use of said memory port.

Claim 29

The method according to claim 26 wherein said system comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD), further comprising the steps of: temporarily storing an address associated with a request to write to said MAU from one of said cache and said IOU if said MAU address bus is not then available to receive said address; temporarily storing write data from said source of said request to write to said MAU if said MAU data bus is not then available to receive said write data; transferring said address associated with said request to write to said MAU from said source of said request to write to said MAU to said switch request bus (SW -- REQ) and said write data associated therewith to said switch write data bus (SW -- RD); transferring said address associated with said request to write to said MAU from said switch request bus (SW -- REQ) to said means for temporarily storing said address associated with said request to write to said MAU; transferring said write data from said switch write data bus (SW -- WD) to said means for temporarily storing said write data; and transferring said address from said means for temporarily storing said address to said MAU address bus and said write data from said means for temporarily storing said write data to said MAU address and write data buses when said MAU address and write data buses are available to receive said address and said write data.

Claim 30

The method according to claim 26 wherein said system comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and said switch network comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD), further comprising the steps of: temporarily storing an address associated with a read request to read data from said from one of said cache and IOU if said MAU address bus is not then available to receive said address; temporarily storing said read data from said MAU if said switch read data bus (SW -- RD) is not then available to transfer said read data; transferring said address associated with said read request from said source of said request to said switch request bus (SW -- REQ) when said switch request bus (SW -- REQ) is available; transferring said address associated with said read request from said switch request bus (SW -- REQ) to said means for temporarily storing said address associated with said read request if said MAU address bus is not then available to receive said address; transferring said read data from said MAU data bus to said means for temporarily storing said read data when said MAU address bus is available to receive said address and said switch read bus (SW -- RD) is not available to transfer said read data; and transferring said read data from said means for temporarily storing said read data to said switch read data bus (SW -- RD) and from said switch read data bus (SW -- RD) to said source of said request when said switch read data bus (SW -- RD) is available to transfer said read data.

Claim 31

The method according to claim 26 wherein said switch network in said system comprises a switch request bus (SW -- REQ) a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD) further comprising the steps of: transferring a request for an I/O data transfer between said cache and said IOU through said switch network and said I/O interface circuit; sending an IOU available signal from said I/O interface circuit to said switch arbitration means when said I/O interface circuit is available to process said request for an I/O data transfer; and transferring an address associated with said request for an I/O data transfer to said I/O interface circuit via said switch request bus (SW -- REQ) when said switch network is available to process said request.

Claim 32

The method according to claim 26 wherein said switch network in said system comprises a switch request bus (SW -- REQ), a switch write data bus (SW -- WD), and a switch read data bus (SW -- RD), further comprising the steps of: transferring write data from said cache to said I/O interface circuit via said switch write data bus (SW -- WD) when said request for an I/O data transfer is a write request; and transferring read data from said IOU circuit to said cache via said switch read data bus (SW -- RD) when said request for an I/O data transfer is a read request.

Claim 33

The method according to claim 26 wherein said system comprises means for coupling said MCU to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and a test and set bypass circuit, said test and set bypass circuit having a snoop address generator coupled to said MAU address bus for generating snoop addresses corresponding to addresses on said MAU address bus and a content addressable memory (CAM), comprising the steps of: storing the address of a semaphore associated with a shared memory region in said CAM; comparing said snoop addresses with the contents of said CAM on subsequent requests for said semaphore; and sending a semaphore failed signal to the source of said request for said semaphore if said semaphore address is still resident in said CAM to thereby save memory bandwidth.

Claim 34

The method according to claim 31, further comprising the steps of: releasing said semaphore and clearing said CAM in response to a write to said shared memory region.

Claim 35

The method according to claim 26, including the step of arbitrating for said switch network according to one of the following arbitration schemes: (a) a slave priority scheme based on a requested device including the step of assigning priority to the memory ports first and then to said IOU in a round robin fashion; and (b) a master priority based on a requesting device including the step of assigning priority to said IOU and then to said cache.

Claim 36

The method according to claim 33, further including the step of assigning highest priority to an intervention request.

Claim 37

The method according to claim 33, wherein one of said microprocessors in said multiprocessor architecture includes an instruction (I) cache and an instruction prefetch buffer, and wherein the method further includes the steps of: determining whether the prefetch buffer in will soon be empty; and if so assigning higher priority to I-cache requests than IOU and D-cache requests.