EP0222074A2
Expired / Lapsed
EP
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An arbitration apparatus for determining priority of access to a shared bus
Assignee: International Business Machines Corp
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Filing: 1986-08-12
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Granted: —
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Expires: 2006-08-12
Abstract
Abstract An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters (10i1, 10i2) arranged in a particular configuration wherein the individual arbiters are located according to their relative priority. Each arbiter has a request terminal (REQ) for receiving access request signals, requesting access to a shared system bus, and an enable terminal for receiving an enabling signal. The enabling signal is generated if access requests are not received by higher arbiters in the particular configuration relative to the specific arbiter. If an arbiter is energized by coincidence of an access request signal and an enabling signal, an access grant signal is developed. If more than one access request signal energizes the arbiter at the same time, a command rotor (10i1b, 10i3b), connected to the arbiter, determines the priority of access of the request signals to the shared bus in response to the "rotation" of the command rotor. If the access request signal is of a predetermined type, a pre-emptive grant signal may be developed from its arbiter even in the absence of an access request if there are no higher requests and no lower grants. If a refresh request is received by an arbiter when its enabling signal is not received, the refresh request is latched, and a refresh takes place when the enabling signal is finally generated.
Inventors
- 👤 Carl Albert Malmquist
- 👤 John David Wilson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
An arbitration apparatus in a computer system with a plurality of subunits (10 b,c) requesting access to a shared resource (bus 10f), the arbitration apparatus comprising: a plurality of individual arbiter means (10i1, 10i2) arranged in a sequence of priority, each of the arbiter means having a request terminal (REQ) adapted for receiving an access request signal from at least one of said subunits seeking access to the shared bus and an enable terminal adapted for receiving an enabling signal, said enabling signal being energized when said access request signal has not energized the request terminal of a higher priority arbiter means in said sequence, whereby an arbiter means develops a grant signal for access to said shared bus when said enabling signal energizes its enable terminal.
Claim 2
Dependent Claim
127 words
An arbitration apparatus in a computer system with a plurality of subunits (10 b,c) requesting access to a shared resource (bus 10f), the arbitration apparatus comprising: a plurality of individual arbiter means (10i1, 10i2) arranged in a sequence of priority, each of the arbiter means having a request terminal (REQ) adapted for receiving an access request signal from at least one of said subunits seeking access to the shared bus and an enable terminal adapted for receiving an enabling signal, said enabling signal being energized when said access request signal has not energized the request terminal of a higher priority arbiter means in said sequence, whereby an arbiter means develops a grant signal for access to said shared bus when said enabling signal energizes its enable terminal.
Claim 3
Dependent Claim
39 words
The arbitration apparatus of claim 1, wherein said access request signal energizing the request terminal of said one of said arbiter means comprises a plurality of access request signals corresponding to a subset of said plurality of said subunits.
Claim 4
Dependent Claim
89 words
The arbitration apparatus of claim 2, further comprising: command storage means (b2a-b2n) connected to said one of said arbiter means (10i1; 10i3) for storing a plurality of identification symbols therein identifying the members of said subset, said command storage means sequentially developing a plurality of output signals indicative of said plurality of identification symbols, said one of said arbiter means granting to said plurality of access request signals sequential access to said shared bus in response to the sequentially developed plurality of output signals from said command storage means.
Claim 5
Dependent Claim
66 words
The arbitration apparatus of claim 3, wherein said plurality of identification symbols may be selectively changed to form a new set of identification symbols identifying the members of a new subset of said plurality of subunits, the time a particular subunit is granted access to the shared bus being dependant upon the number of times its corresponding identification symbol is stored in said command storage means.
Claim 6
Dependent Claim
194 words
The arbitration apparatus of one of the claims 1-4, further comprising: gate means (10i4c) connected to an output of said one of said arbiter means (10i4) and responsive to said grant signal from said one of said arbiter means, to a "no higher requests" signal indicating that no access request signal energizes an arbiter means which is higher in said sequence, and to a "no lower grants" signal indicating that no grant signal is developed from an arbiter means which is lower in said sequence for developing a further grant signal granting access to said shared bus in response to said grant signal from said one of said arbiter means and for developing a pre-emptive grant signal granting access to said shared bus in the absence of a said access request signal energizing the request terminal of said one of said arbiter means in response to said "no higher requests" signal and to said "no lower grants" signal, said one of said arbiter means having immediate access to said shared bus after said pre-emptive grant signal is developed when said access request signal energizes the request terminal of said one of said arbiter means.
Claim 7
Dependent Claim
28 words
The arbitration apparatus of claim 5, wherein said access request signal is an Instruction cache request signal developed from an Instruction Cache subunit disposed within said computer system.
Claim 8
Dependent Claim
147 words
The arbitration apparatus of one of the claims 1-6, further comprising: latch circuit means (10i7d) connected to an input of said one of said arbiter means and responsive to said access request signal and to said enabling signal for developing a set signal when said access request signal is received by said one of said arbiter means and said enabling signal is not received by said one of said arbiter means; and gating means (10i8) connected to an output of said latch circuit means and responsive to said set signal and to an "allow arbitration" signal for developing an access grant signal, granting access to said shared bus, when said set signal and said "allow arbitration" signal is received by said gating means, said "allow arbitration" signal being generated and energizing said gating means when said enabling signal is received by said one of said arbiter means.
Claim 9
Dependent Claim
62 words
The arbitration apparatus of claim 7, wherein said enabling signal is not received by said one of said arbiter means when an access request signal is being received by said higher arbiter means in said sequence, whereby said access grant signal is developed, granting access to said shared bus, when an access request signal is not received by said higher arbiter means.
Claim 10
Dependent Claim
48 words
The arbitration apparatus of claim 8, wherein said access request signal energizing said one of said arbiter means is a refresh access request signal, said set signal being developed from said latch circuit means being a refresh pending signal, said access grant signal being a refresh grant signal.
References Cited (Backward Citations)
No citation records indexed.
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