Patent US5440705A successfully refreshed from Google Patents.
US5440705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address modulo adjust unit for a memory management unit for monolithic digital signal processor
Assignee: RPX Corp
•
Filing: 1990-04-30
•
Granted: 1995-08-08
•
Expires: 2010-04-30
Abstract
Abstract A memory management unit suitable fo use in a digital signal processor having internal and eternal memories is described. The unit is especially designed to facilitate numeric algorithms such as fast fourier transforms, auto-correlation and digital filtering by relieving the programmer from the need to monitor memory accesses. Automatic post-updating of memory addresses is provided after indirect memory references. Also, memory boundary-checking is performed according to a user-specified modulus value, and a memory reference is automatically adjusted to fall within the user-specified address range. A dual-access register file stores initial memory addresses and their associated modulus values and in a dual-bus embodiment a pair of address generation units provides post-updates of the addresses stored in the register files. Direct addressing of memory is also supported by the memory management unit and a page register internal to the unit allows the user to specify memory page information during a direct address operation. A modulo-adjust portion of the address generation unit implements any user-specified modulii in the range 0 to 64, as well as modulii of 128, 256 and 512. A method of operating a memory management unit to provide the features obtained by the instant invention is also described.
Inventors
- 👤 Bu-Chin Wang
- 👤 Marita E. Daly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/3552; G06F17/00; G06F17/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
525 words
In a memory management having an address register file providing initial address signals, and a modulo register file providing modulii signals, an address modulo-adjust unit comprising: a) means responsive to bits of said initial address signals for generating sum signals representing the sum of signals representing a user-supplied displacement value and a user-specified one of said initial addresses; and b) means responsive to said sum signals and to a user-specified one of said modulii for adjusting said sum signals and for generating a modulo-adjusted address, said address being within a range bounded by said user-specified modulus, said means being responsive to any user specified modulus comprising at least any integer between 0 and 64, wherein said means for adjusting comprises: (i) first modulo address adjust means responsive to bit values in predetermined bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a first range; (ii) second modulo address adjust means responsive said bit values in predetermined bit positions of said sum signals said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a second range; and (iii) multiplexer means coupled to said first and second modulo-adjust address means for selectably providing either said modulus-adjusted address generated by said first or said second modulo-adjust address; wherein said first modulo address means comprises: (a) boundary-check means responsive to bit values in said predetermined bit positions of said sum signals, bit values in predetermined bit positions of said initial address signals and to said user-specified modulus for generating a binary-valued signal indicative of whether said address represented by bit values in said bit positions of said sum signals exceeds said user-specified modulus, and (b) means responsive to said binary-valued signal and bit values in said predetermined bit positions of said sum signals for selectably adding or subtracting said user-specified modulus to said predetermined bit positions of such sum signals and for generating therefrom a set of signals representing said modulus-adjusted address; and wherein said boundary check means comprises: means response to bit values of predetermined bit positions of said user-specified modulus for generating therefrom a set of mask signals; a plurality of AND gates each responsive to bit valves in a predetermined bit position of said initial address signals and to a predetermined one of said mask signals for generating therefrom an output signal; a plurality of OR gates each responsive to a predetermined one of said signals generated by said AND gates and to a predetermined bit position of said user-specified modulus for generating therefrom an output signal; a plurality of multiplexer means each coupled to a predetermined one of said AND gates and a predetermined one of said OR gates for selectably providing a signal, being either said signal generated by said AND gate or said OR gate, in response to a predetermined sign bit position of said user-specified displacement value; and comparator means receiving at a first input said signals provided by said multiplexer-means and at a second input said predetermined bit positions of said sum signals for generating said binary-valued signal.
Claim 2
Dependent Claim
525 words
In a memory management having an address register file providing initial address signals, and a modulo register file providing modulii signals, an address modulo-adjust unit comprising: a) means responsive to bits of said initial address signals for generating sum signals representing the sum of signals representing a user-supplied displacement value and a user-specified one of said initial addresses; and b) means responsive to said sum signals and to a user-specified one of said modulii for adjusting said sum signals and for generating a modulo-adjusted address, said address being within a range bounded by said user-specified modulus, said means being responsive to any user specified modulus comprising at least any integer between 0 and 64, wherein said means for adjusting comprises: (i) first modulo address adjust means responsive to bit values in predetermined bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a first range; (ii) second modulo address adjust means responsive said bit values in predetermined bit positions of said sum signals said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a second range; and (iii) multiplexer means coupled to said first and second modulo-adjust address means for selectably providing either said modulus-adjusted address generated by said first or said second modulo-adjust address; wherein said first modulo address means comprises: (a) boundary-check means responsive to bit values in said predetermined bit positions of said sum signals, bit values in predetermined bit positions of said initial address signals and to said user-specified modulus for generating a binary-valued signal indicative of whether said address represented by bit values in said bit positions of said sum signals exceeds said user-specified modulus, and (b) means responsive to said binary-valued signal and bit values in said predetermined bit positions of said sum signals for selectably adding or subtracting said user-specified modulus to said predetermined bit positions of such sum signals and for generating therefrom a set of signals representing said modulus-adjusted address; and wherein said boundary check means comprises: means response to bit values of predetermined bit positions of said user-specified modulus for generating therefrom a set of mask signals; a plurality of AND gates each responsive to bit valves in a predetermined bit position of said initial address signals and to a predetermined one of said mask signals for generating therefrom an output signal; a plurality of OR gates each responsive to a predetermined one of said signals generated by said AND gates and to a predetermined bit position of said user-specified modulus for generating therefrom an output signal; a plurality of multiplexer means each coupled to a predetermined one of said AND gates and a predetermined one of said OR gates for selectably providing a signal, being either said signal generated by said AND gate or said OR gate, in response to a predetermined sign bit position of said user-specified displacement value; and comparator means receiving at a first input said signals provided by said multiplexer-means and at a second input said predetermined bit positions of said sum signals for generating said binary-valued signal.
Claim 3
Dependent Claim
367 words
In a memory management unit having an address register file providing initial address signals, and a modulo register file providing modulii signals, an address modulo-adjust unit comprising: a) means responsive to bits of said initial address signals for generating sum signals representing the sum of signals representing a user-supplied displacement value and a user-specified one of said initial addresses; and b) means responsive to said sum signals and to a user-specified one of said modulii for adjusting said sum signals and for generating a modulo-adjusted address, said address being Within a range bounded by said user-specified modulus, said means being responsive to any user specified modulus comprising at least any integer between 0 and 64; wherein said means for adjusting comprises: (i) first modulo address adjust means responsive to bit values in predetermine bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a first range; (ii) second modulo address adjust means responsive said bit values in predetermined bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified values in a second range; and (iii) multiplexer means coupled to said first and second modulo-adjust address means for selectably providing either said modulus-adjusted address generated by said first or said second modulo-adjust address means wherein said second modulo-adjust address means comprises: a plurality of AND gates each responsive to bit values in predetermined bit positions of signals representing said user-specified modulus for generating therefrom an output signal; a plurality of multiplexer means each coupled to a predetermined one of said AND gates for selectably providing a signal being either a predetermined bit position of said sum signals or a predetermined bit position of said initial address signals, in response to said signal generated by said predetermined AND gate; and multiplexer means coupled to a predetermined bit position of said signals representing said user-specified modulus for selectably providing a signal being either a predetermined bit position of said sum signals or a predetermined bit position of said initial address signals, in response to said signal representing said predetermined bit position of said user-specified modulus.
Claim 4
Dependent Claim
367 words
In a memory management unit having an address register file providing initial address signals, and a modulo register file providing modulii signals, an address modulo-adjust unit comprising: a) means responsive to bits of said initial address signals for generating sum signals representing the sum of signals representing a user-supplied displacement value and a user-specified one of said initial addresses; and b) means responsive to said sum signals and to a user-specified one of said modulii for adjusting said sum signals and for generating a modulo-adjusted address, said address being Within a range bounded by said user-specified modulus, said means being responsive to any user specified modulus comprising at least any integer between 0 and 64; wherein said means for adjusting comprises: (i) first modulo address adjust means responsive to bit values in predetermine bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified modulii values in a first range; (ii) second modulo address adjust means responsive said bit values in predetermined bit positions of said sum signals, said initial address signals and said user-specified modulus for providing said modulo-adjusted address for user-specified values in a second range; and (iii) multiplexer means coupled to said first and second modulo-adjust address means for selectably providing either said modulus-adjusted address generated by said first or said second modulo-adjust address means wherein said second modulo-adjust address means comprises: a plurality of AND gates each responsive to bit values in predetermined bit positions of signals representing said user-specified modulus for generating therefrom an output signal; a plurality of multiplexer means each coupled to a predetermined one of said AND gates for selectably providing a signal being either a predetermined bit position of said sum signals or a predetermined bit position of said initial address signals, in response to said signal generated by said predetermined AND gate; and multiplexer means coupled to a predetermined bit position of said signals representing said user-specified modulus for selectably providing a signal being either a predetermined bit position of said sum signals or a predetermined bit position of said initial address signals, in response to said signal representing said predetermined bit position of said user-specified modulus.
Claim 5
Dependent Claim
54 words
In the memory management unit according to claim 2, an address modulo-adjust unit wherein an adding/subtracting means is further responsive to a predetermined sign bit position of said user-specified displacement value, whereby addition or subtraction is undertaken responsive to said binary-valued signal generated by said boundary check means and to said sign bit position.
References Cited (Backward Citations)
US3883853A
Cited
US4056819A
Cited
US4150434A
Cited
US4169289A
Cited
US4202305A
Cited
US4456953A
Cited
US4627017A
Cited
US4594687A
Cited
US4689738A
Cited
US4584666A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |