Address range determination

Claim 1

A circuit for checking to see if a memory address made up of a group of M high order digits plus a group of K low order digits can fall within a range of contiguous memory addresses comprising: first means for receiving the low order K-digits of an address at one end of said range of contiguous addresses, second means for receiving c-digits that indicate the number of addresses in said range of contiguous addresses, first logic means responsive both to the K-g high order digits of said K low order digits received in said first means where g is a number of digits less than K digits and equal to or greater than c digits and to the correspondingly ordered K-g high order digits of said lower order digits in the memory address being checked to test for the existence of conditions of the K-g digits which would indicate the memory address can fall within said range and in response to the test provide a first set of signals indicative of the results of the test, second logic means responsive both to said low-order g digits of said K low order digits received in said first means, and to the correspondingly ordered g low order digits of the memory address being checked and also responsive to said c digits received by said second means for testing the occurrence of a particular one of a plurality of further conditions of the g digits which would indicate that the memory address can fall within the range and provide a second set of signals indicative to the results of the testing, and third logic means responsive to the first and second set of signals from said first and second logic means respectively to determine concurrence of one of the plurality of further conditions with one of the first mentioned conditions and thereby indicate whether said memory address does fall in said range.