Patent US5440241A successfully refreshed from Google Patents.
US5440241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby
Assignee: Micron Technology Inc
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Filing: 1992-03-06
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Granted: 1995-08-08
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Expires: 2012-03-06
Abstract
Abstract A method for probe testing and burning-in integrated circuits formed within dice or chips on a silicon wafer and then optionally either: (1) dicing the wafer into individual chips for shipment or (2) mating the wafer for shipment with a facing substrate having a temperature coefficient of expansion (TCE) matching the TCE of the wafer. Advantageously, the facing substrate is used for both probe and burn-in operations as well as being made a part of the wafer package in option No. 2 above where either the whole silicon wafer or a partial silicon wafer meeting threshold die requirements is to be shipped. In addition, probe and burn-in operations are carried out rapidly at high yields only after all integrated circuit manufacture has been completed.
Inventors
- 👤 Jerrold L. King
- 👤 Jerry M. Brooks
- 👤 Warren M. Farnworth
- 👤 George P. McGill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:35
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R1/00; G01R1/02; G01R1/04; H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; H10W; H10W78/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
A method for testing and burning-in dice on a silicon wafer and for packaging the wafer, which comprises the steps of: a. forming die contacts on said dice for receiving test and burn-in signals, b. forming a mating substrate out of a material having a temperature coefficient of expansion matching that of said silicon wafer, and having an interconnect pattern with contacts in a geometrical configuration matching the geometrical configuration of said die contacts on said dice, c. bringing said substrate contacts into physical and electrical connection with said die contacts, d. applying test and burn-in signals to said die contacts by way of said substrate contacts, e. maintaining said mating substrate and silicon wafer permanently in place after testing and burn-in of said silicon wafer, f. packaging said mating substrate and silicon wafer into a packaged assembly by encapsulation of said substrate and wafer with an encapsulating material, and g. using said wafer in memory applications with said mating substrate supporting said silicon wafer and electrically connecting said die contacts to external circuitry for providing read/write and control operations.
Claim 2
Independent Claim
180 words
A method for testing and burning-in dice on a silicon wafer and for packaging the wafer, which comprises the steps of: a. forming die contacts on said dice for receiving test and burn-in signals, b. forming a mating substrate out of a material having a temperature coefficient of expansion matching that of said silicon wafer, and having an interconnect pattern with contacts in a geometrical configuration matching the geometrical configuration of said die contacts on said dice, c. bringing said substrate contacts into physical and electrical connection with said die contacts, d. applying test and burn-in signals to said die contacts by way of said substrate contacts, e. maintaining said mating substrate and silicon wafer permanently in place after testing and burn-in of said silicon wafer, f. packaging said mating substrate and silicon wafer into a packaged assembly by encapsulation of said substrate and wafer with an encapsulating material, and g. using said wafer in memory applications with said mating substrate supporting said silicon wafer and electrically connecting said die contacts to external circuitry for providing read/write and control operations.
Claim 3
Dependent Claim
166 words
A process for probe testing and burning in a plurality of integrated circuit dice on an integrated circuit wafer and for packaging the wafer, said method comprising the steps of: forming a substrate out of a material having a temperature coefficient of expansion that matches a temperature coefficient of expansion of said wafer; forming an interconnect pattern on the substrate, said interconnect pattern including contacts in a geometrical configuration that matches a geometrical configuration of contact pads formed on the dice; bringing the substrate contacts into electrical communication with the contact pads on the dice; testing the dice by applying test and burn-in signals through the substrate interconnect pattern and contacts to the contact pads; following testing leaving the substrate and wafer in electrical communication; packaging the wafer and substrate into a packaged assembly by encapsulation of said substrate and wafer with an encapsulating material; and connecting the interconnect pattern of the substrate to external read/write and control circuitry for using the wafer in memory applications.
Claim 4
Dependent Claim
166 words
A process for probe testing and burning in a plurality of integrated circuit dice on an integrated circuit wafer and for packaging the wafer, said method comprising the steps of: forming a substrate out of a material having a temperature coefficient of expansion that matches a temperature coefficient of expansion of said wafer; forming an interconnect pattern on the substrate, said interconnect pattern including contacts in a geometrical configuration that matches a geometrical configuration of contact pads formed on the dice; bringing the substrate contacts into electrical communication with the contact pads on the dice; testing the dice by applying test and burn-in signals through the substrate interconnect pattern and contacts to the contact pads; following testing leaving the substrate and wafer in electrical communication; packaging the wafer and substrate into a packaged assembly by encapsulation of said substrate and wafer with an encapsulating material; and connecting the interconnect pattern of the substrate to external read/write and control circuitry for using the wafer in memory applications.
Claim 5
Dependent Claim
33 words
The method as claimed in claim 2 and wherein the substrate is formed of a material selected from the group of materials consisting of aluminum oxide, monocrystalline silicon, amorphous glass and polycrystalline silicon.
Claim 6
Dependent Claim
36 words
The method as claimed in claim 2 and wherein a Z-axis conductive pad is placed between the wafer and substrate to establish electrical communication between the contacts on the substrate and contact pads on the dice.
Claim 7
Dependent Claim
34 words
The method as claimed in claim 2 and wherein packaging is by encapsulating using a process selected from the group consisting of fluidized bed encapsulation, transfer molding encapsulation and potting with a curable compound.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |