Enhanced planarization technique for an integrated circuit

Claim 2

An integrated circuit fabrication method, comprising the steps of: (a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points; (b.) applying and curing spin-on glass, to form a first dielectric; (c.) depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer; (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; (e.) performing a global etchback to substantially remove said dielectric stack from said high points of said partially fabricated structure; (f.) deposition of an interlevel dielectric; (g.) etching holes in said interlevel dielectric in locations; and (h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

Claim 3

The method of claim 1, wherein said deposition step (c.) is plasma-enhanced.

Claim 4

The method of claim 1, wherein said deposition step (c.) uses TEOS as a source gas.

Claim 5

The method of claim 1, comprising the additional step of applying a passivating dielectric, under vacuum conditions, after said step (a.) and before said deposition step (b.).

Claim 6

The method of claim 1, wherein said deposition step (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.

Claim 7

The method of claim 1, wherein said deposition step (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.

Claim 8

The method of claim 1, wherein said interlevel dielectric is a doped silicate glass.

Claim 9

An integrated circuit fabrication method, comprising the steps of: (a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points; (b.) applying and curing spin-on glass, to form a first dielectric; (c.) depositing silicon dioxide under vacuum conditions, to form a second dielectric layer over said first layer; (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; (e.) performing a global etchback to substantially remove said dielectric stack from said high points of said partially fabricated structure; (f.) deposition of an interlevel dielectric; (g.) etching holes in said interlevel dielectric in locations; and (h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

Claim 10

An integrated circuit fabrication method, comprising the steps of: (a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points; (b.) applying and curing spin-on glass, to form a first dielectric; (c.) depositing silicon dioxide under vacuum conditions, to form a second dielectric layer over said first layer; (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; (e.) performing a global etchback to substantially remove said dielectric stack from said high points of said partially fabricated structure; (f.) deposition of an interlevel dielectric; (g.) etching holes in said interlevel dielectric in locations; and (h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

Claim 11

The method of claim 8, wherein said deposition step (c.) is plasma-enhanced.

Claim 12

The method of claim 8, wherein said deposition step (c.) uses TEOS as a source gas.

Claim 13

The method of claim 8, comprising the additional step of applying a passivating dielectric, under vacuum conditions, after said step (a.) and before said deposition step (b.).

Claim 14

The method of claim 8, wherein said deposition step (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.

Claim 15

The method of claim 8, wherein said deposition step (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.

Claim 16

The method of claim 8, wherein said interlevel dielectric is a doped silicate glass.

Claim 17

An integrated circuit fabrication method, comprising the steps of: (a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points; (b.) applying and curing spin-on glass, to form a first dielectric layer; (c.) depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer, said second dielectric layer having a thickness equal to or less than said first layer; (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer; (e.) performing a global etchback to substantially remove said dielectric stack from said high points of said partially fabricated structure; (f.) deposition of an interlevel dielectric; (g.) etching holes in said interlevel dielectric in locations; and (h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

Claim 18

An integrated circuit fabrication method, comprising the steps of: (a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points; (b.) applying and curing spin-on glass, to form a first dielectric layer; (c.) depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer, said second dielectric layer having a thickness equal to or less than said first layer; (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer; (e.) performing a global etchback to substantially remove said dielectric stack from said high points of said partially fabricated structure; (f.) deposition of an interlevel dielectric; (g.) etching holes in said interlevel dielectric in locations; and (h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

Claim 19

The method of claim 15, wherein said deposition step (c.) is plasma-enhanced.

Claim 20

The method of claim 15, wherein said deposition step (c.) uses TEOS as a source gas.

Claim 21

The method of claim 15, comprising the additional step of applying a passivating dielectric, under vacuum conditions, after said step (a.) and before said deposition step (b.).

Claim 22

The method of claim 15, wherein said deposition step (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.

Claim 23

The method of claim 15, wherein said interlevel dielectric is a doped silicate glass.

Claim 24

The method of claim 15, wherein said deposition step (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å inclusive.