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US5432740A
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Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure
Assignee: Texas Instruments Inc
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Filing: 1993-10-12
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Granted: 1995-07-11
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Expires: 2013-10-12
Abstract
Abstract A EEPROM memory array (10) includes a plurality of memory cells (24) which are connected in a symmetric array between row lines (26) and Column Lines (28) and Virtual Ground Lines (29). Each of the memory cells includes a merged pass gate which is connected to a control gate. A non-stacked structure is utilized wherein a floating gate (42) is formed, having two portions that extend over an active region, a tunnel diode portion (44) and a control gate portion (46). The floating gate portion (44) is disposed over a thin tunnel oxide layer (47) to form a tunnel diode which allows Fowler-Nordheim tunneling to occur. The control gate portion (46) is disposed over a much thicker oxide layer such that tunneling does not occur. A control gate layer (50) is disposed over the floating gate (42) such that it overlaps the edges thereof and encloses the floating gate (42). On the one side of the floating gate (42), the control gate extends over the gate oxide layer in an extended portion (52) to form a pass gate structure. The pass gate structure is a merged structure formed in series with the floating gate cell. The merged pass gate has a controllable threshold that allows the floating gate cell to be overerased without causing unwanted conduction when the cell is unselected.
Inventors
- 👤 Iano D'Arrigo
- 👤 Georges Falessi
- 👤 Michael C. Smayling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:34
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
219 words
A Flash EEPROM memory having a memory array of EEPROM memory cells arranged in rows and columns on the face of a semiconductor substrate of a first conductivity type, the memory cells each comprising: an active region having a channel region defined therein; a source region defined in said active region on one side of said channel region; a drain region formed on the other side of said channel region opposite said source region; a floating gate structure having a control gate portion extending over a first portion of said channel region and a tunnel diode portion extending over a second portion of said channel region; a tunnel oxide layer disposed between said tunnel diode portion and said channel region to allow for Fowler-Nordheim electron tunneling therethrough; a gate oxide layer disposed between said control gate portion and said channel region; and a control gate structure having a first portion disposed over said floating gate structure and separated therefrom by a layer of interlevel oxide, and having a second portion that extends from said first portion of said control gate structure over a portion of said channel region, such that said second portion of said control gate structure forms a pass transistor in series with a floating gate cell formed by said first portion of said control gate structure.
Claim 2
Dependent Claim
219 words
A Flash EEPROM memory having a memory array of EEPROM memory cells arranged in rows and columns on the face of a semiconductor substrate of a first conductivity type, the memory cells each comprising: an active region having a channel region defined therein; a source region defined in said active region on one side of said channel region; a drain region formed on the other side of said channel region opposite said source region; a floating gate structure having a control gate portion extending over a first portion of said channel region and a tunnel diode portion extending over a second portion of said channel region; a tunnel oxide layer disposed between said tunnel diode portion and said channel region to allow for Fowler-Nordheim electron tunneling therethrough; a gate oxide layer disposed between said control gate portion and said channel region; and a control gate structure having a first portion disposed over said floating gate structure and separated therefrom by a layer of interlevel oxide, and having a second portion that extends from said first portion of said control gate structure over a portion of said channel region, such that said second portion of said control gate structure forms a pass transistor in series with a floating gate cell formed by said first portion of said control gate structure.
Claim 3
Dependent Claim
27 words
The memory of claim 1, wherein the tunnel diode portion of said floating gate structure extends over a portion of said channel region adjacent said drain region.
Claim 4
Dependent Claim
111 words
The memory of claim 2, wherein said drain region comprises: a first doped region of a second conductivity type material opposite to the first conductivity type material and abutting said channel region; a tunnel diode region doped with said second conductivity type material and disposed adjacent to said first doped region; a second doped region of said second conductivity type material disposed adjacent said tunnel diode region opposite said first doped region, said tunnel diode portion of said floating gate structure extending over said tunnel diode region and separated therefrom by said tunnel oxide layer wherein said tunnel diode region has a higher resistance than said first and second doped regions.
Claim 5
Dependent Claim
32 words
The memory of claim 1, wherein said floating gate structure includes a coupling portion disposed between said tunnel diode portion and said control gate portion and disposed outside of said active region.
Claim 6
Dependent Claim
17 words
The memory of claim 1, wherein said gate oxide layer is thicker than said tunnel oxide layer.
Claim 7
Dependent Claim
53 words
The memory of claim 1, wherein said floating gate structure comprises a first layer of polycrystalline silicon material and said control gate structure comprises a second layer of polycrystalline silicon material and wherein said second polycrystalline silicon layer overlaps substantially all edges of said first polycrystalline silicon layer forming said floating gate structure.
Claim 8
Dependent Claim
52 words
The memory of claim 1, wherein said floating gate structure comprises a first layer of conductive material and said control gate structure comprises a second layer of conductive material wherein the width of said overlapping portion of said control gate structure is greater than three times the thickness of said first layer.
Claim 9
Dependent Claim
39 words
The memory of claim 1, wherein said overlapping portion of said control gate structure extends outward from said floating gate structure on the opposite side of said channel region from said tunnel diode portion of said floating gate structure.
Claim 10
Dependent Claim
90 words
The memory of claim 1, wherein said active region is disposed in a first tank of first conductivity type material that is biased at a voltage to prevent reverse biasing of the semiconductor junction between any of said source or drain regions and said tank; and said first tank disposed within a second tank of second conductivity type material to separate said first tank from the substrate, said second tank biased at a voltage to prevent forward biasing of the semiconductor junction between said first tank and said second tank.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-10 | 1999-01-09 | 1999-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-10 | 2003-01-09 | 2003-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-10 | 2007-01-09 | 2007-07-11 | $7700.00 | Window Closed / Lapsed |