Patent US5432467A successfully refreshed from Google Patents.
US5432467A
Expired / Lapsed
US
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Programmable logic device with low power voltage level translator
Assignee: Altera Corp
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Filing: 1994-10-17
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Granted: 1995-07-11
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Expires: 2014-10-17
Abstract
Abstract A voltage translation circuit 6 and method of operating a circuit to provide voltage level translation, particularly for use in association with a programmable logic device 2. An input signal, is provided to an NMOS transistor N2 and a CMOS inverter 12. The inverter 12 drives an NMOS pulldown transistor N4. The drain of N2 is coupled to the input of an inverter 14, the output of which is also coupled to the translation circuit output. A source of PMOS pullup transistor P1 drives the input of inverter 14 to pullup the output to a high level.
Inventors
- 👤 Srinivas T. Reddy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
A reprogrammable logic device comprising: a reprogrammable logic circuit, said reprogrammable logic circuit having a plurality of inputs and a logic output, said logic output being a combinatorial function of said inputs, said logic output varying between about ground and a first higher voltage level; a voltage level translator coupled to said logic output, said voltage level translator comprising: a first NMOS transistor having its gate coupled to said logic output, a source coupled to ground, and a drain coupled to a first node; a first CMOS inverter having an input coupled to said logic output, output of said first CMOS inverter coupled to a gate of a NMOS pulldown transistor, said NMOS pulldown transistor having a source coupled to ground and a drain coupled to an output of said voltage level translator; a first PMOS transistor having a drain coupled to said first node, a source coupled to a voltage source having a second lower voltage level, and a gate coupled to said output of said voltage level translator; and a second CMOS inverter having an input coupled to said first node and an output coupled to said output of said voltage level translator; and an output buffer having an input coupled to said output of said voltage level translator, and an output coupled to an output pin of said reprogrammable logic circuit.
Claim 2
Dependent Claim
224 words
A reprogrammable logic device comprising: a reprogrammable logic circuit, said reprogrammable logic circuit having a plurality of inputs and a logic output, said logic output being a combinatorial function of said inputs, said logic output varying between about ground and a first higher voltage level; a voltage level translator coupled to said logic output, said voltage level translator comprising: a first NMOS transistor having its gate coupled to said logic output, a source coupled to ground, and a drain coupled to a first node; a first CMOS inverter having an input coupled to said logic output, output of said first CMOS inverter coupled to a gate of a NMOS pulldown transistor, said NMOS pulldown transistor having a source coupled to ground and a drain coupled to an output of said voltage level translator; a first PMOS transistor having a drain coupled to said first node, a source coupled to a voltage source having a second lower voltage level, and a gate coupled to said output of said voltage level translator; and a second CMOS inverter having an input coupled to said first node and an output coupled to said output of said voltage level translator; and an output buffer having an input coupled to said output of said voltage level translator, and an output coupled to an output pin of said reprogrammable logic circuit.
Claim 3
Dependent Claim
19 words
The reprogrammable logic device of claim 1 wherein said first NMOS transistor is larger than said first PMOS transistor.
Claim 4
Dependent Claim
225 words
A reprogrammable logic device comprising: a reprogrammable logic circuit, said reprogrammable logic circuit having a plurality of inputs and a logic output, said logic output being a combinatorial function of said inputs, said logic output varying between about ground and a first higher voltage level; a voltage level translator coupled to said logic output, said voltage level translator consisting of: a first NMOS transistor having its gate coupled to said logic output, a source coupled to ground, and a drain coupled to a first node; a first CMOS inverter having an input coupled to said logic output, output of said first CMOS inverter coupled to a gate of a NMOS pulldown transistor, said NMOS pulldown transistor having a source coupled to ground and a drain coupled to an output of said voltage level translator; a first PMOS transistor having a drain coupled to said first node, a source coupled to a voltage source having a second lower voltage level, and a gate coupled to said output of said voltage level translator; and a second CMOS inverter having an input coupled to said first node and an output coupled to said output of said voltage level translator; and an output buffer having an input coupled to said output of said voltage level translator, and an output coupled to an output pin of said reprogrammable logic circuit.
Claim 5
Dependent Claim
225 words
A reprogrammable logic device comprising: a reprogrammable logic circuit, said reprogrammable logic circuit having a plurality of inputs and a logic output, said logic output being a combinatorial function of said inputs, said logic output varying between about ground and a first higher voltage level; a voltage level translator coupled to said logic output, said voltage level translator consisting of: a first NMOS transistor having its gate coupled to said logic output, a source coupled to ground, and a drain coupled to a first node; a first CMOS inverter having an input coupled to said logic output, output of said first CMOS inverter coupled to a gate of a NMOS pulldown transistor, said NMOS pulldown transistor having a source coupled to ground and a drain coupled to an output of said voltage level translator; a first PMOS transistor having a drain coupled to said first node, a source coupled to a voltage source having a second lower voltage level, and a gate coupled to said output of said voltage level translator; and a second CMOS inverter having an input coupled to said first node and an output coupled to said output of said voltage level translator; and an output buffer having an input coupled to said output of said voltage level translator, and an output coupled to an output pin of said reprogrammable logic circuit.
Claim 6
Dependent Claim
19 words
The reprogrammable logic device of claim 3 wherein said first NMOS transistor is larger than said first PMOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-10 | 1999-01-09 | 1999-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-10 | 2003-01-09 | 2003-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-10 | 2007-01-09 | 2007-07-11 | $7700.00 | Window Closed / Lapsed |