Pin diode driver circuit for radar system

Claim 2

A timing delay circuit comprising: a first transistor having a control electrode coupled to an input terminal, a reference electrode coupled to a first DC bias terminal and an output electrode coupled to an output terminal of said timing delay circuit; a second transistor having a control electrode coupled to said input terminal, a reference electrode coupled to a second DC bias terminal and an output electrode; and a third transistor having a control electrode coupled to said output electrode of said second transistor, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to the output terminal of said timing delay circuit.

Claim 3

The timing delay circuit of claim 1 wherein said transistors are bi-polar junction transistors and said control electrodes correspond to base electrodes said reference electrodes correspond to collector electrodes and said output electrodes correspond to emitter electrodes.

Claim 4

The timing delay circuit of claim 2 wherein said collector and emitter regions of said first transistor having a dopant of a first conductive type and said base region of said first transistor has a dopant of a second conductive type; and said collector and emitter regions of said second and third transistors have a dopant of the second conductive type and said base region of said second and third transistors has a dopant of the first conductive type.

Claim 5

The timing delay circuit of claim 3 further comprising: a first resistor having a first electrode coupled to said output electrode of said first transistor and a second electrode coupled to said output terminal of said timing delay circuit; and a second resistor having a first electrode coupled to said output electrode of said second transistor and a second electrode coupled to said output electrode of said third transistor.

Claim 6

A driver circuit comprising: a voltage translator circuit having an input terminal and an output terminal with said input terminal being coupled to an input terminal of said driver circuit; a current amplification circuit having an input terminal and an output terminal with said input terminal of said current amplification circuit being coupled to said output terminal of said voltage translator circuit; and a timing delay circuit having an input terminal and an output terminal with said input terminal of said timing delay circuit coupled to said output terminal of said current amplification circuit and said output terminal of said timing delay circuit coupled to an output terminal of said driver circuit; said timing delay circuit further comprising: a first transistor having a control electrode coupled to the input terminal of the timing delay circuit, a reference electrode coupled to a first DC bias terminal and an output electrode coupled to said output port of said timing delay circuit; a second transistor having a control electrode coupled to the input terminal of the timing delay circuit, a reference electrode coupled to a second DC bias terminal and an output electrode; and a third transistor having a control electrode coupled to said output electrode of said second transistor, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to said second output port of said timing delay circuit.

Claim 7

A driver circuit comprising: a voltage translator circuit having an input terminal and an output terminal with said input terminal being coupled to an input terminal of said driver circuit; a current amplification circuit having an input terminal and an output terminal with said input terminal of said current amplification circuit being coupled to said output terminal of said voltage translator circuit; and a timing delay circuit having an input terminal and an output terminal with said input terminal of said timing delay circuit coupled to said output terminal of said current amplification circuit and said output terminal of said timing delay circuit coupled to an output terminal of said driver circuit; said timing delay circuit further comprising: a first transistor having a control electrode coupled to the input terminal of the timing delay circuit, a reference electrode coupled to a first DC bias terminal and an output electrode coupled to said output port of said timing delay circuit; a second transistor having a control electrode coupled to the input terminal of the timing delay circuit, a reference electrode coupled to a second DC bias terminal and an output electrode; and a third transistor having a control electrode coupled to said output electrode of said second transistor, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to said second output port of said timing delay circuit.

Claim 8

The driver circuit of claim 5 wherein said voltage translator circuit comprises: a fourth transistor having a control electrode coupled to said input terminal of said voltage translator circuit, a reference electrode coupled to the first DC bias terminal, and an output electrode coupled to said output terminal of said voltage translator circuit; and a fifth transistor having a control electrode coupled to said input terminal of said voltage translator circuit, a reference electrode coupled to the second DC bias terminal and an output electrode coupled to said output terminal of said voltage translator circuit.

Claim 9

The driver circuit of claim 6 wherein said current amplification circuit comprises: a sixth transistor having a control electrode coupled to said input terminal of said current amplification circuit, a reference electrode coupled to said first DC bias terminal and an output electrode coupled to said output port of said current amplification circuit; and a seventh transistor having a control electrode coupled to said input terminal of said current amplification circuit, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to said output port of said current amplification circuit.

Claim 10

The timing delay circuit of claim 7 wherein said transistors are bi-polar junction transistors and said control electrodes correspond to base electrodes said reference electrodes correspond to collector electrodes and said output electrodes correspond to emitter electrodes.

Claim 11

The timing delay circuit of claim 8 wherein said collector and emitter regions of said first transistor having a dopant of a first conductive type and said base region of said first transistor has a dopant of a second conductive type; and said collector and emitter regions of said second and third transistors have a dopant of the second conductive type and said base region of said second and third transistors has a dopant of the first conductive type.

Claim 12

The driver circuit of claim 9 wherein said timing delay circuit further comprises: a first resistor having a first electrode coupled to said output electrode of said first transistor and a second electrode coupled to said output port of said timing delay circuit; and a second resistor having a first electrode coupled to said output electrode of said second transistor and a second electrode coupled to said output electrode of said third transistor.

Claim 13

A driver circuit having a pair of input terminals, and an output terminal comprising: a line receiver having a pair of input electrodes coupled to said input terminals and an output electrode; a charge coupled device driver having an input electrode and an output electrode with said input electrode of said charge coupled device driver coupled to said output electrode of said line receiver; a voltage translator circuit having an input terminal and an output terminal with said input terminal of said voltage transistor circuit being coupled to said output electrode of said charge coupled device driver; a current amplification circuit having an input terminal and an output terminal with said input terminal of said current amplification circuit being coupled to said output terminal of said voltage translator circuit; and a timing delay circuit having an input terminal and an output terminal with said input terminal of said timing delay circuit coupled to said output terminal of said current amplification circuit and said output terminal of said timing delay circuit coupled to said output terminal of said driver circuit.

Claim 14

A driver circuit having a pair of input terminals, and an output terminal comprising: a line receiver having a pair of input electrodes coupled to said input terminals and an output electrode; a charge coupled device driver having an input electrode and an output electrode with said input electrode of said charge coupled device driver coupled to said output electrode of said line receiver; a voltage translator circuit having an input terminal and an output terminal with said input terminal of said voltage transistor circuit being coupled to said output electrode of said charge coupled device driver; a current amplification circuit having an input terminal and an output terminal with said input terminal of said current amplification circuit being coupled to said output terminal of said voltage translator circuit; and a timing delay circuit having an input terminal and an output terminal with said input terminal of said timing delay circuit coupled to said output terminal of said current amplification circuit and said output terminal of said timing delay circuit coupled to said output terminal of said driver circuit.

Claim 15

The driver circuit of claim 11 wherein said voltage translator circuit comprises: a first transistor having a control electrode coupled to said input terminal of said voltage translator circuit, a reference electrode coupled to a first DC bias terminal of said driver circuit, and an output electrode coupled to said output terminal of said voltage translator circuit; and a second transistor having a control electrode coupled to said input terminal of said voltage translator circuit, a reference electrode coupled to a second DC bias terminal of said driver circuit and an output electrode coupled to said output terminal of said voltage translator circuit.

Claim 16

The driver circuit of claim 12 wherein said current amplification circuit comprises: a third transistor having a control electrode coupled to said input terminal of said first current amplification circuit, a reference electrode coupled to said first DC bias terminal and an output electrode coupled to said output terminal of said current amplification circuit; and a fourth transistor having a control electrode coupled to said input terminal of said current amplification circuit, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to said output terminal of said current amplification circuit.

Claim 17

The driver circuit of claim 13 wherein said timing delay circuit comprises: a fifth transistor having a control electrode coupled to said input terminal, a reference electrode coupled to said first DC bias terminal and an output electrode coupled to said output port of said timing delay circuit; a sixth transistor having a control electrode coupled to said input terminal, a reference electrode coupled to said second DC bias terminal and an output electrode; and a seventh transistor having a control electrode coupled to said output electrode of said second transistor, a reference electrode coupled to said second DC bias terminal and an output electrode coupled to said second output port of said timing delay circuit.

Claim 18

The timing delay circuit of claim 14 wherein said transistors are bi-polar junction transistor and said control electrodes correspond to base electrodes said reference electrodes correspond to collector electrodes and said output electrodes correspond to emitter electrodes.

Claim 19

The timing delay circuit of claim 15 wherein said collector and emitter regions of said fifth transistor having a dopant of a first conductive type and said base region of said fifth transistor has a dopant of a second conductive type; and said collector and emitter regions of said sixth and seventh transistors have a dopant of the second conductive type and said base region of said sixth and seventh transistors has a dopant of the first conductive type.

Claim 20

The driver circuit of claim 16 wherein said timing delay circuit further comprises: a first resistor having a first electrode coupled to said output electrode of said fifth transistor and a second electrode coupled to said output terminal of said timing delay circuit; and a second resistor having a first electrode coupled to said output electrode of said sixth transistor and a second electrode coupled to said output electrode of said seventh transistor.