US5428808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single-chip microcomputer
Assignee: Renesas Electronics Corp
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Filing: 1994-03-25
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Granted: 1995-06-27
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Expires: 2014-03-25
Abstract
Abstract A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
Inventors
- 👤 Terumi Sawase
- 👤 Kouki Noguchi
- 👤 Hideo Nakamura
- 👤 Yasushi Akao
- 👤 Shiro Baba
- 👤 Yoshimune Hagiwara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
176 words
A programmable circuit device formed on a single chip, to be used with a processor and a read only memory, wherein the processor has a data bus and an address bus and wherein the processor has an address space defined by a bit width of the address bus, and wherein the read only memory stores programs, said programmable circuit comprising: a logic circuit having a writing circuit which is configured to couple with said data bus, a selecting circuit which is configured to couple with said address bus and having a plurality of non-volatile memory elements coupled to the selecting circuit, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing data into said plurality of nonvolatile memory elements, wherein a writing operation of said plurality of non-volatile memory elements in said logic circuit is executed from an external device by designating said plurality of non-volatile memory elements in said logic circuit by an address signal from the external device to the selecting circuit of the programmable circuit device.
Claim 2
Dependent Claim
176 words
A programmable circuit device formed on a single chip, to be used with a processor and a read only memory, wherein the processor has a data bus and an address bus and wherein the processor has an address space defined by a bit width of the address bus, and wherein the read only memory stores programs, said programmable circuit comprising: a logic circuit having a writing circuit which is configured to couple with said data bus, a selecting circuit which is configured to couple with said address bus and having a plurality of non-volatile memory elements coupled to the selecting circuit, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing data into said plurality of nonvolatile memory elements, wherein a writing operation of said plurality of non-volatile memory elements in said logic circuit is executed from an external device by designating said plurality of non-volatile memory elements in said logic circuit by an address signal from the external device to the selecting circuit of the programmable circuit device.
Claim 3
Dependent Claim
63 words
A programmable circuit device according to claim 1, wherein said logic circuit comprises: a non-volatile memory which includes the plurality of non-volatile memory elements and which stores instructions; a control circuit providing control signals in response to an instruction read out from the non-volatile memory; and a circuit having an operation which is controlled by the control signals provided from the control circuit.
Claim 4
Dependent Claim
48 words
A programmable circuit device according to claim 2, wherein said logic circuit further comprises: a storing circuit which is coupled to said non-volatile memory and which stores a next address data to be supplied to the non-volatile memory; and a program sequence generator coupled to the storing circuit.
Claim 5
Dependent Claim
22 words
A programmable circuit device according to claim 3, wherein the processor and the read only memory are formed on said single chip.
Claim 6
Dependent Claim
24 words
A programmable circuit device according to claim 1, wherein said selecting circuit includes an address decoder decoding the address signal from the external device.
Claim 7
Independent Claim
149 words
A system comprising: a data bus; an address bus; a read only memory which stores programs; a processor coupled to the data bus and to the address bus; and a logic circuit having a writing circuit which is configured to couple with said data bus, a selecting circuit which is configured to couple with said address bus and having a plurality of non-volatile memory elements coupled to the writing circuit and to the selecting circuit, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing data into said plurality of non-volatile memory elements; wherein a writing operation of said plurality of non-volatile memory elements in said logic circuit is executed from an external device by designating said plurality of non-volatile memory elements in said logic circuit by an address signal from the external device to the selecting circuit of the logic circuit.
Claim 8
Independent Claim
149 words
A system comprising: a data bus; an address bus; a read only memory which stores programs; a processor coupled to the data bus and to the address bus; and a logic circuit having a writing circuit which is configured to couple with said data bus, a selecting circuit which is configured to couple with said address bus and having a plurality of non-volatile memory elements coupled to the writing circuit and to the selecting circuit, and having a programmable variable logical construction, the programmable variable logical construction being programmed by electrically writing data into said plurality of non-volatile memory elements; wherein a writing operation of said plurality of non-volatile memory elements in said logic circuit is executed from an external device by designating said plurality of non-volatile memory elements in said logic circuit by an address signal from the external device to the selecting circuit of the logic circuit.
Claim 9
Dependent Claim
60 words
A system according to claim 6, wherein said logic circuit comprises: a non-volatile memory which includes the plurality of non-volatile memory elements and which stores instructions; a control circuit providing control signals in response to an instruction read out from the non-volatile memory; and a circuit of which an operation is controlled by the control signals from the control circuit.
Claim 10
Dependent Claim
45 words
A system according to claim 7, wherein said logic circuit further comprises: a storing circuit which is coupled to said non-volatile memory and which stores next address data to be supplied to the non-volatile memory; and a program sequence generator coupled to the storing circuit.
Claim 11
Dependent Claim
16 words
A system according to claim 6, wherein said logic circuit is formed on a single chip.
Claim 12
Dependent Claim
20 words
A system according to claim 9, wherein said processor and said read only memory are formed on said single chip.
Claim 13
Dependent Claim
22 words
A system according to claim 9, wherein said selecting circuit includes an address decoder decoding the address signal from the external device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |