Semiconductor device having retrograde well and diffusion-type well

Claim 2

A semiconductor memory device having a semiconductor substrate with a main surface, said substrate including; a first region formed in said main surface and having a first isolation field oxide formed on said main surface, said first isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said first isolation field oxide having a first thickness in a direction normal to said main surface, a first impurity concentration profile with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface and underlying said first isolation field oxide, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth >said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak; and a second region formed in said main surface independently of said first region and having a second isolation field oxide formed on said main surface, said second isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, and a second impurity concentration profile with impurity concentration monotonically decreasing as depth from said main surface increases.

Claim 3

The semiconductor memory device according to claim 1 wherein, said first region comprises a retrograde well region formed in a main portion of said main surface of said semiconductor substrate, and said second region comprises a diffusion-type well region formed in a peripheral portion of said main surface of said semiconductor substrate.

Claim 4

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for accessing said plurality of memory cells for writing and reading of said information; and a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a first isolation field oxide formed on said main surface, said first isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said first isolation field oxide having a first thickness in a direction normal to said main surface, a first impurity concentration profile with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface and underlying said first isolation field oxide having a first thickness, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak; and a second region formed in said main surface independently of said first region and having a second isolation field oxide formed on said main surface, said second isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, and a second impurity concentration profile with impurity concentration monotonically decreasing as depth from said main surface increases, wherein said first region includes at least a portion of said memory cell portion and said circuit portion, and said second region includes at least a portion of said peripheral circuit portion and no portion of said memory cell portion and said circuit portion.

Claim 5

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for accessing said plurality of memory cells for writing and reading of said information; and a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a first isolation field oxide formed on said main surface, said first isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said first isolation field oxide having a first thickness in a direction normal to said main surface, a first impurity concentration profile with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface and underlying said first isolation field oxide having a first thickness, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak; and a second region formed in said main surface independently of said first region and having a second isolation field oxide formed on said main surface, said second isolation field oxide separating and isolating semiconductor devices formed within said semiconductor substrate from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, and a second impurity concentration profile with impurity concentration monotonically decreasing as depth from said main surface increases, wherein said first region includes at least a portion of said memory cell portion and said circuit portion, and said second region includes at least a portion of said peripheral circuit portion and no portion of said memory cell portion and said circuit portion.

Claim 6

The semiconductor memory device according to claim 3 wherein, said first region comprises a retrograde well region formed in a main portion of said main surface of said semiconductor substrate, and said second region comprises a diffusion-type well region formed in a peripheral portion of said main surface of said semiconductor substrate.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for accessing said plurality of memory cells for writing and reading of said information; and a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a first impurity concentration profile of a first impurity type with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak, a second region formed in said main surface and having a second impurity concentration profile of a second impurity type with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a second depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak, a third region formed in said main surface and having a third impurity concentration profile of said first impurity type with impurity concentration monotonically decreasing as depth from said main surface increases, a fourth region formed in said main surface and having a fourth impurity concentration profile of said second impurity type with impurity concentration monotonically decreasing as depth from said main surface increases, a first isolation field oxide formed on said main surface, said first isolation field oxide separating and isolating semiconductor devices, formed within said semiconductor substrate in the first and second regions, from each other in directions parallel to said main surface with the second concentration peak at a second depth of each region underlying a respective portion of said first isolation field oxide, said first isolation field oxide having a first thickness in a direction normal to said main surface, and a second isolation field oxide formed on said main surface, said second isolation field oxide separating and isolating semiconductor devices, formed within said semiconductor substrate in the third and fourth regions, from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, wherein, said first, second, third and fourth regions are formed independently of each other, said first and second regions include said memory cell array, and said third and fourth regions include said peripheral circuit portion.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for accessing said plurality of memory cells for writing and reading of said information; and a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a first impurity concentration profile of a first impurity type with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak, a second region formed in said main surface and having a second impurity concentration profile of a second impurity type with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a second depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak, a third region formed in said main surface and having a third impurity concentration profile of said first impurity type with impurity concentration monotonically decreasing as depth from said main surface increases, a fourth region formed in said main surface and having a fourth impurity concentration profile of said second impurity type with impurity concentration monotonically decreasing as depth from said main surface increases, a first isolation field oxide formed on said main surface, said first isolation field oxide separating and isolating semiconductor devices, formed within said semiconductor substrate in the first and second regions, from each other in directions parallel to said main surface with the second concentration peak at a second depth of each region underlying a respective portion of said first isolation field oxide, said first isolation field oxide having a first thickness in a direction normal to said main surface, and a second isolation field oxide formed on said main surface, said second isolation field oxide separating and isolating semiconductor devices, formed within said semiconductor substrate in the third and fourth regions, from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, wherein, said first, second, third and fourth regions are formed independently of each other, said first and second regions include said memory cell array, and said third and fourth regions include said peripheral circuit portion.

Claim 9

The semiconductor memory device according to claim 5 wherein, said first and second regions comprise retrograde well regions formed in a main portion of said main surface of said semiconductor substrate, said third and fourth regions comprise diffusion-type well regions formed in a peripheral portion of said main surface of said semiconductor substrate, and said memory cell array comprises a plurality of CMOS memory cells including pairs of transistors formed in respective retrograde well regions.

Claim 10

The semiconductor memory device according to claim 5 further comprising: a plurality of first and second MOS transistors, wherein said first and second regions are retrograde-type well regions, and said third and fourth regions are diffusion-type well regions, said array of memory cells is formed in said retrograde-type well regions and includes said first MOS transistors, and said peripheral circuit is formed in said diffusion well regions and includes said second MOS transistors.

Claim 11

A semiconductor memory device comprising: a semiconductor substrate having a main surface; and a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for writing and reading of said information; a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a plurality of first wells each having a first impurity concentration profile with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak; and a second region formed in said main surface independently of said first region and having a plurality of second wells each having a second impurity concentration profile with impurity concentration monotonically decreasing as depth from said main surface increases; said first region including at least a portion of said memory cell portion and said circuit portion, and said second region including at least a portion of said peripheral circuit portion and no portion of said memory cell portion and said circuit portion, a plurality of first isolation field oxides formed on said main surface, said plurality of first isolation field oxides separating and isolating semiconductor devices, formed within said semiconductor substrate of said memory cell portion and said circuit portion, from each other in directions parallel to said main surface, said plurality of first isolation field oxides having a first thickness in a direction normal to said main surface, and a plurality of second isolation field oxides formed on said main surface, said plurality of second isolation field oxides separating and isolating semiconductor devices, formed within said semiconductor substrate of said peripheral circuit portion, from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, wherein an isolation field oxide having a first thickness is formed between each of the plurality of first wells of said first region with the second concentration peak at a second depth of each well underlying a respective portion of said isolation field oxide, and an isolation field oxide having a second thickness is formed between each of the plurality of second wells of said second region.

Claim 12

A semiconductor memory device comprising: a semiconductor substrate having a main surface; and a memory cell portion having a plurality of memory cells arranged for storing information; a circuit portion for writing and reading of said information; a peripheral circuit portion for performing a predetermined circuit operation; said semiconductor substrate including a first region formed in said main surface and having a plurality of first wells each having a first impurity concentration profile with a first concentration peak at a first depth beneath said main surface, a second concentration peak at a second depth beneath said main surface, and a third concentration peak at a third depth beneath said main surface, said first depth>said second depth>said third depth, and said first concentration peak>said third concentration peak and said first concentration peak>said second concentration peak; and a second region formed in said main surface independently of said first region and having a plurality of second wells each having a second impurity concentration profile with impurity concentration monotonically decreasing as depth from said main surface increases; said first region including at least a portion of said memory cell portion and said circuit portion, and said second region including at least a portion of said peripheral circuit portion and no portion of said memory cell portion and said circuit portion, a plurality of first isolation field oxides formed on said main surface, said plurality of first isolation field oxides separating and isolating semiconductor devices, formed within said semiconductor substrate of said memory cell portion and said circuit portion, from each other in directions parallel to said main surface, said plurality of first isolation field oxides having a first thickness in a direction normal to said main surface, and a plurality of second isolation field oxides formed on said main surface, said plurality of second isolation field oxides separating and isolating semiconductor devices, formed within said semiconductor substrate of said peripheral circuit portion, from each other in directions parallel to said main surface, said second isolation field oxide having a second thickness, greater than the first thickness, in a direction normal to said main surface, wherein an isolation field oxide having a first thickness is formed between each of the plurality of first wells of said first region with the second concentration peak at a second depth of each well underlying a respective portion of said isolation field oxide, and an isolation field oxide having a second thickness is formed between each of the plurality of second wells of said second region.