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US5427962A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a thin film transistor

Assignee: Casio Computer Co Ltd
•
Filing: 1992-11-10
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Granted: 1995-06-27
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Expires: 2012-11-10
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Abstract

Abstract A method of manufacturing a thin-film transistor which comprises the steps of forming a gate electrode on an insulating substrate, a gate insulating film covering the gate electrode, and an i-type a-Si layer on the gate insulating film, forming a blocking film made of metal such as Cr or the like on a channel-forming region of the i-type a-Si layer, and forming an n-type a-Si layer covering the i-type a-Si layer and the blocking film, forming a metal layer on the n-type a-Si layer, and etching a predetermined portion of the n-type a-Si layer and a predetermined portion of the metal layer, thereby forming a source electrode and a drain electrode. That portion of the blocking film which is located below a gap between the source electrode and the drain electrode is removed from the i-type a-Si layer.

Inventors

  • 👤 Makoto Sasaki
  • 👤 Hiromitsu Ishii
  • 👤 Kazuhiro Sasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 14:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; Y; Y10; Y10S; Y10S438/00; Y10S438/911

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 174 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film of silicon nitride covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of oxidizing a surface of said intrinsic amorphous silicon layer, thereby forming a silicon oxide film; a third step of forming a metal layer on said silicon oxide film; a fourth step of etching said metal layer, forming a part of the metal layer covering a channel region of said intrinsic amorphous silicon layer; a fifth step of removing an exposed portion of said silicon oxide film; a sixth step of forming a conductive layer covering said intrinsic amorphous silicon layer and said metal layer, and etching a portion of the conductive layer, thereby forming source and drain electrodes and a portion of the conductive layer disposed between the source and drain electrodes; and a seventh step of removing a portion of said metal layer on the channel region.
Claim 2
Independent Claim 174 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film of silicon nitride covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of oxidizing a surface of said intrinsic amorphous silicon layer, thereby forming a silicon oxide film; a third step of forming a metal layer on said silicon oxide film; a fourth step of etching said metal layer, forming a part of the metal layer covering a channel region of said intrinsic amorphous silicon layer; a fifth step of removing an exposed portion of said silicon oxide film; a sixth step of forming a conductive layer covering said intrinsic amorphous silicon layer and said metal layer, and etching a portion of the conductive layer, thereby forming source and drain electrodes and a portion of the conductive layer disposed between the source and drain electrodes; and a seventh step of removing a portion of said metal layer on the channel region.
Claim 3
Independent Claim 157 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating substrate, a gate insulating film covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel-forming region of said intrinsic amorphous silicon layer; a third step of forming an n-type amorphous silicon layer covering said intrinsic amorphous silicon layer and said blocking film, forming a metal layer on the n-type amorphous silicon layer, and etching a portion of the n-type amorphous silicon layer and a portion of the metal layer, thereby forming a source electrode and a drain electrode; and a fourth step of anodically oxidizing that portion of said blocking film which is located below a gap between said source electrode and said drain electrode, thereby changing the portion of said blocking film into an insulating metal oxide film.
Claim 4
Independent Claim 157 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating substrate, a gate insulating film covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel-forming region of said intrinsic amorphous silicon layer; a third step of forming an n-type amorphous silicon layer covering said intrinsic amorphous silicon layer and said blocking film, forming a metal layer on the n-type amorphous silicon layer, and etching a portion of the n-type amorphous silicon layer and a portion of the metal layer, thereby forming a source electrode and a drain electrode; and a fourth step of anodically oxidizing that portion of said blocking film which is located below a gap between said source electrode and said drain electrode, thereby changing the portion of said blocking film into an insulating metal oxide film.
Claim 5
Dependent Claim 43 words
The method according to claim 2, wherein said fourth step comprises a step of applying a voltage to said drain electrode, thereby anodizing that portion of said blocking film which is located below a gap between said source electrode and said drain electrode.
Claim 6
Dependent Claim 69 words
The method according to claim 2, which further comprises a step of forming a data line connected to said drain electrode, for supplying a data signal to the thin-film transistor, and in which said fourth step includes a step of applying a voltage from the data line, thereby anodizing that portion of said blocking film which is located below a gap between said source electrode and said drain electrode.
Claim 7
Independent Claim 177 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel-forming region of said intrinsic amorphous silicon layer, a metal silicide layer being formed in the channel-forming region of the intrinsic amorphous silicon layer; a third step of forming and etching a portion of the conductive layer, thereby forming a source electrode and a drain electrode; a fourth step of removing a portion of said blocking film which is located below a gap between said source electrode and said drain electrode; a fifth step of removing a region of the metal silicide layer on the channel forming region; and wherein said fifth step includes, a first sub-step of oxidizing the metal silicide layer on the channel-forming region which was exposed in the fourth step; and a second sub-step of removing the oxidized metal silicide layer.
Claim 8
Independent Claim 177 words
A method of manufacturing a thin-film transistor, comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel-forming region of said intrinsic amorphous silicon layer, a metal silicide layer being formed in the channel-forming region of the intrinsic amorphous silicon layer; a third step of forming and etching a portion of the conductive layer, thereby forming a source electrode and a drain electrode; a fourth step of removing a portion of said blocking film which is located below a gap between said source electrode and said drain electrode; a fifth step of removing a region of the metal silicide layer on the channel forming region; and wherein said fifth step includes, a first sub-step of oxidizing the metal silicide layer on the channel-forming region which was exposed in the fourth step; and a second sub-step of removing the oxidized metal silicide layer.
Claim 9
Dependent Claim 24 words
The method according to claim 5, wherein said first sub-step includes an oxidizing step of oxidizing the metal silicide layer throughout its whole thickness.
Claim 10
Dependent Claim 25 words
The method according to claim 5, wherein said second sub-step includes a step of removing the oxidized metal silicide layer using a hydrofluoric acid-based etchant.
Claim 11
Dependent Claim 26 words
The method according to claim 5, wherein said fourth step includes a step of removing the portion of said blocking film using a non-hydrofluoric acid-based etchant.
Claim 12
Dependent Claim 32 words
The method according to claim 1, wherein said conductive layer includes a n-type amorphous silicon layer covering said intrinsic amorphous silicon layer and a metal film on the n-type amorphous silicon layer.
Claim 13
Dependent Claim 32 words
The method according to claim 1, wherein said fifth step is performed using an etchant for which an etching rate of the silicon oxide film is greater than that of silicon nitride.
Claim 14
Dependent Claim 30 words
The method according to claim 1, wherein said fourth step is performed using an etchant for which an etching rate of the metal is greater than that of silicon nitride.
Claim 15
Dependent Claim 21 words
The method according to claim 1, wherein said fifth step is performed using an etchant including a hydrofluoric acid based etchant.
Claim 16
Dependent Claim 20 words
The method according to claim 1, wherein said fourth step is performed using an etchant including a non-hydrofluoric acid-based etchant.
Claim 17
Dependent Claim 18 words
The method according to claim 1, wherein said silicon oxide film has a thickness of about 10 nm.
Claim 18
Dependent Claim 33 words
The method according to claim 1, wherein said conductive layer includes an n-type amorphous silicon layer covering said intrinsic amorphous silicon layer and a metal film formed on the n-type amorphous silicon layer.
Claim 19
Independent Claim 125 words
A method of manufacturing a thin film transistor comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film of silicon nitride covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel region of said semiconductor layer; a third step of forming a conductive layer overlying said semiconductor layer and said blocking film, and etching a portion of the conductive layer so as to form a source electrode and a drain electrode; and a fourth step of anodizing a portion of said blocking film located on said channel region thereby electrically separating the source and drain regions from each other.
Claim 20
Independent Claim 125 words
A method of manufacturing a thin film transistor comprising: a first step of forming a gate electrode on an insulating member, a gate insulating film of silicon nitride covering the gate electrode, and an intrinsic amorphous silicon layer on the gate insulating film; a second step of forming a blocking film made of metal on a channel region of said semiconductor layer; a third step of forming a conductive layer overlying said semiconductor layer and said blocking film, and etching a portion of the conductive layer so as to form a source electrode and a drain electrode; and a fourth step of anodizing a portion of said blocking film located on said channel region thereby electrically separating the source and drain regions from each other.

References Cited (Backward Citations)

US4459739A Cited
JPS62213278A Cited
JPS6425482A Cited
US5091337A Cited
US5053354A Cited
JPH01302865A Cited
JPH02199842A Cited
JPH02297969A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-06-26 1998-12-26 1999-06-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-06-26 2002-12-26 2003-06-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-06-26 2006-12-26 2007-06-27 $7700.00 Window Closed / Lapsed

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