US5091337A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing amorphous-silicon thin-film transistors
Assignee: Seiko Precision Inc
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Filing: 1990-11-01
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Granted: 1992-02-25
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Expires: 2010-11-01
Abstract
Abstract A method for manufacturing an amorphous silicon thin film transistor in which a gate insulating layer is provided over a gate on a substrate. An amorphous silicon layer is formed on the gate insulating layer, and a protective insulating layer is formed on the amorphous silicon layer. A pattern conforming to the gate is applied to the protective layer, and the amorphous layer is exposed in regions outside of the pattern. A doped silicon layer is then added, and source and drain electrodes formed to partly overlap the remaining protective insulating layer.
Inventors
- 👤 Yoshiaki Watanabe
- 👤 Sakae Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; Y; Y10; Y10S; Y10S148/00; Y10S148/105
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
142 words
A method of manufacturing amorphous-silicon thin-film transistors, comprising the steps of: forming a gate insulating layer on an insulating substrate on which a gate electrode having a predetermined configuration is formed; forming an amorphous-silicon layer on said gate insulating layer; forming a protective insulating layer on said amorphous-silicon layer; imparting a pattern conforming to said gate electrode to said protective insulating layer while exposing said amorphous-silicon layer at regions outside of said pattern; coating said protective insulating layer and said amorphous-silicon layer with a silicon layer containing impurities serving as the donor and acceptor; forming a source electrode and a drain electrode in such a manner that they partly overlap said protective insulating layer; and then simultaneously removing said impurity containing silicon layer and said amorphous-silicon layer using said source electrode and drain electrode as a mask, to form an island structure.
Claim 2
Independent Claim
142 words
A method of manufacturing amorphous-silicon thin-film transistors, comprising the steps of: forming a gate insulating layer on an insulating substrate on which a gate electrode having a predetermined configuration is formed; forming an amorphous-silicon layer on said gate insulating layer; forming a protective insulating layer on said amorphous-silicon layer; imparting a pattern conforming to said gate electrode to said protective insulating layer while exposing said amorphous-silicon layer at regions outside of said pattern; coating said protective insulating layer and said amorphous-silicon layer with a silicon layer containing impurities serving as the donor and acceptor; forming a source electrode and a drain electrode in such a manner that they partly overlap said protective insulating layer; and then simultaneously removing said impurity containing silicon layer and said amorphous-silicon layer using said source electrode and drain electrode as a mask, to form an island structure.
Claim 3
Dependent Claim
71 words
A method of manufacturing amorphous-silicon thin-film transistors as claimed in claim 1 comprising the steps of radiating the back surface of said insulating substrate with light so as to expose photoresist applied to said protective insulating layer and removing said protective insulating layer using a photoresist pattern which is obtained by developing said photoresist as the mask, thereby imparting to said protective insulating layer a pattern conforming to said gate electrode.
Claim 4
Dependent Claim
27 words
A method of manufacturing amorphous-silicon thin-film transistors as claimed in claim 1 comprising the step of forming said source electrode and drain electrode from a metal layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |