Patent US5422301A successfully refreshed from Google Patents.
US5422301A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor device with MOSFET
Assignee: Fujitsu Ltd
•
Filing: 1994-10-17
•
Granted: 1995-06-06
•
Expires: 2014-10-17
Abstract
Abstract A method of manufacturing a semiconductor device with MOSFETs including the steps of forming an anti-oxidation film pattern over an element forming region of a semiconductor substrate, selectively oxidizing a region not covered with the anti-oxidation film pattern on the semiconductor substrate to form an isolating oxide film, and implanting impurities into the semiconductor substrate via the isolating oxide film and anti-oxidation film at a predetermined acceleration energy to form a threshold voltage control region under the anti-oxidation film and a channel stop region under the isolating oxide film. The channel stop region and threshold voltage control region can be formed by a single ion implantation process.
Inventors
- 👤 Yoshimichi Otsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:40
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
90 words
A method of manufacturing a semiconductor device comprising the steps of: forming an anti-oxidation film pattern over an element forming region of a semiconductor substrate; selectively oxidizing a region not covered with said anti-oxidation film pattern on said semiconductor substrate to form an isolation oxide film; and implanting first impurity ions into said semiconductor substrate via said isolation oxide film and said anti-oxidation film at a first acceleration energy to form a threshold voltage control region under said anti-oxidation film and a channel stop region under said isolation oxide film.
Claim 2
Independent Claim
90 words
A method of manufacturing a semiconductor device comprising the steps of: forming an anti-oxidation film pattern over an element forming region of a semiconductor substrate; selectively oxidizing a region not covered with said anti-oxidation film pattern on said semiconductor substrate to form an isolation oxide film; and implanting first impurity ions into said semiconductor substrate via said isolation oxide film and said anti-oxidation film at a first acceleration energy to form a threshold voltage control region under said anti-oxidation film and a channel stop region under said isolation oxide film.
Claim 3
Dependent Claim
33 words
A method according to claim 1, wherein an impurity concentration at the surface of said channel stop region is higher than an impurity concentration at the surface of said threshold voltage control region.
Claim 4
Dependent Claim
49 words
A method according to claim 1, wherein said semiconductor substrate has a surface layer formed of a polycrystalline semiconductor layer, said anti-oxidation film pattern is formed on said polycrystalline semiconductor layer, and said isolation oxide film forming step oxidizes said polycrystalline layer not covered with said anti-oxidation film pattern.
Claim 5
Dependent Claim
68 words
A method according to claim 1, further comprising, before said step of implanting ions to form said threshold voltage control region and said channel stop region, the step of implanting second impurity ions of the same conductivity type as said impurities into the semiconductor substrate via said isolation oxide film and said anti-oxidation film at a higher acceleration energy than said first acceleration energy to form a well.
Claim 6
Dependent Claim
30 words
A method according to claim 4, wherein said well has a graded impurity concentration distribution lowering with decrease in depth from a depth position toward said threshold voltage controlling region.
Claim 7
Dependent Claim
49 words
A method according to claim 2, wherein said semiconductor substrate has a surface layer formed of a polycrystalline semiconductor layer, said anti-oxidation film pattern is formed on said polycrystalline semiconductor layer, and said isolation oxide film forming step oxidizes said polycrystalline layer not covered with said anti-oxidation film pattern.
Claim 8
Dependent Claim
49 words
A method according to claim 4, wherein said semiconductor substrate has a surface layer formed of a polycrystalline semiconductor layer, said anti-oxidation film pattern is formed on said polycrystalline semiconductor layer, and said isolation oxide film forming step oxidizes said polycrystalline layer not covered with said anti-oxidation film pattern.
Claim 9
Dependent Claim
30 words
A method according to claim 7, wherein said well has a graded impurity concentration distribution lowering with decrease in depth from a depth position toward said threshold voltage controlling region.
Claim 10
Dependent Claim
30 words
A method according to claim 1, wherein said semiconductor substrate has a surface layer formed of an oxide film, and said anti-oxidation film pattern is formed on said oxide film.
Claim 11
Dependent Claim
35 words
A method according to claim 1, wherein said semiconductor substrate has a surface laminate formed of an oxide film and a polycrystalline semiconductor layer, and said anti-oxidation film pattern is formed on said surface laminate.
Claim 12
Dependent Claim
81 words
A method according to claim 1, wherein said impurity ions in said impurity ion implanting step have a second conductivity type, further comprising, after said isolation oxide film forming step, the steps of: forming a first resist mask having an opening defining a second conductivity type well region, and by using said first resist mask, implanting second conductivity type ions in said semiconductor substrate via said anti-oxidation film pattern and said isolation oxide film to form a second conductivity type well.
Claim 13
Dependent Claim
138 words
A method according to claim 1, wherein said impurity ions in said impurity ion implanting step have a second conductivity type, further comprising, after said isolation oxide film forming step, the steps of: forming a first resist mask having an opening defining a region for forming a first conductivity type transistor, the first conductivity type being opposite to said second conductivity type; and by using said first resist mask, implanting second conductivity type ions at a high acceleration energy to form a second conductivity type well in said first conductivity type transistor forming region, wherein by using said first resist mask as a mask, said step of implanting ions to form said threshold voltage control region and said channel stop region implants ions of said second conductivity type in said semiconductor substrate at a relatively low acceleration energy.
Claim 14
Dependent Claim
74 words
A method according to claim 12, further comprising the steps of: removing said first resist mask; forming a second resist mask having an opening defining a region for forming a second conductivity type transistor; and by using said second resist mask as a mask, implanting ions of first conductivity type into said semiconductor substrate at a high acceleration energy to form a first conductivity type well in said second conductivity type transistor forming region.
Claim 15
Dependent Claim
72 words
A method according to claim 13, further comprising the step of, by using said same second resist mask as a mask, implanting ions of said first conductivity type into said second conductivity type transistor forming region via said isolation oxide film and said anti-oxidation film at a relatively low acceleration energy to form a threshold voltage control region under said anti-oxidation film and a channel stop region under said isolation oxide film.
References Cited (Backward Citations)
US4422885A
Cited
US4574467A
Cited
US4717683A
Cited
JPS6489463A
Cited
US5348910A
Cited
US5358890A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-05 | 1998-12-05 | 1999-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-05 | 2002-12-05 | 2003-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-05 | 2006-12-05 | 2007-06-06 | $7700.00 | Window Closed / Lapsed |