Method of operating a data processing apparatus to compute correlation

Claim 1

A method of computing a mean squared error between a predetermined plural number of pairs of first and second values using a data processing apparatus including an arithmetic logic unit generating a selected arithmetic combination of two multibit inputs and a status register that stores a status bit indicating whether a prior arithmetic combination of said arithmetic logic unit was less than zero, said method comprising the steps of: 1) for each pair of first and second values a) employing said arithmetic logic unit to subtract said second value from said first value, thereby forming a difference, b) storing said status bit in said status register indicating whether said difference was less than zero, c) employing said arithmetic logic unit to conditionally either add said difference to zero if said status bit indicates said difference was not less than zero or subtract said difference from zero if said status bit indicates said difference was less than zero, thereby forming an absolute value of said difference, d) multiplying said absolute value by itself, thereby forming a product, e) employing said arithmetic logic unit to add said product to a prior running sum, thereby forming a new running sum; and 2) dividing a final running sum for all of said plurality of pairs by said predetermined number.

Claim 2

A method of computing a mean squared error between a predetermined plural number of pairs of first and second values using a data processing apparatus including an arithmetic logic unit generating a selected arithmetic combination of two multibit inputs and a status register that stores a status bit indicating whether a prior arithmetic combination of said arithmetic logic unit was less than zero, said method comprising the steps of: 1) for each pair of first and second values a) employing said arithmetic logic unit to subtract said second value from said first value, thereby forming a difference, b) storing said status bit in said status register indicating whether said difference was less than zero, c) employing said arithmetic logic unit to conditionally either add said difference to zero if said status bit indicates said difference was not less than zero or subtract said difference from zero if said status bit indicates said difference was less than zero, thereby forming an absolute value of said difference, d) multiplying said absolute value by itself, thereby forming a product, e) employing said arithmetic logic unit to add said product to a prior running sum, thereby forming a new running sum; and 2) dividing a final running sum for all of said plurality of pairs by said predetermined number.

Claim 5

A method of computing a mean squared error between a predetermined plural number of pairs of first and second values using a data processing apparatus including an arithmetic logic unit generating a selected arithmetic combination of first and second multibit inputs, said arithmetic logic unit divided into a plurality of N sections, each section generating said selected arithmetic combination of respective subsets of said first and second multibit inputs and a multiple flags register that stores N status bits, one for each of said N sections of said arithmetic logic unit indicating whether a prior arithmetic combination of said corresponding section of said arithmetic logic unit was less than zero, said method comprising the steps of: 1) repetitively performing the following substeps: a) employing said arithmetic logic unit to simultaneously subtract each of a next N of said second values from respective ones of a next N of said first values, thereby forming N differences, b) storing said N status bits in said multiple flags register indicating respectively whether said N differences were less than zero, c) employing said arithmetic logic unit to conditionally for each of said N differences either add a particular one of said N differences to zero if said corresponding status bit indicates said difference was not less than zero or subtract said particular one of said N differences from zero if said corresponding status bit indicates said difference was less than zero, thereby forming N absolute values of said N differences, d) multiplying each of said N absolute values by itself, thereby forming N products, e) employing said arithmetic logic unit to add each of said N products to a corresponding one of N prior running sums, thereby forming N new running sums; until each of said plurality of pairs of first and second values are processed; 2) employing said arithmetic logic unit to add a final running sum of each of said N running sums, thereby forming a combined final running sum; and 3) dividing said combined final running sum for all of said plurality of pairs by said predetermined number.

Claim 6

A method of computing a mean squared error between a predetermined plural number of pairs of first and second values using a data processing apparatus including an arithmetic logic unit generating a selected arithmetic combination of first and second multibit inputs, said arithmetic logic unit divided into a plurality of N sections, each section generating said selected arithmetic combination of respective subsets of said first and second multibit inputs and a multiple flags register that stores N status bits, one for each of said N sections of said arithmetic logic unit indicating whether a prior arithmetic combination of said corresponding section of said arithmetic logic unit was less than zero, said method comprising the steps of: 1) repetitively performing the following substeps: a) employing said arithmetic logic unit to simultaneously subtract each of a next N of said second values from respective ones of a next N of said first values, thereby forming N differences, b) storing said N status bits in said multiple flags register indicating respectively whether said N differences were less than zero, c) employing said arithmetic logic unit to conditionally for each of said N differences either add a particular one of said N differences to zero if said corresponding status bit indicates said difference was not less than zero or subtract said particular one of said N differences from zero if said corresponding status bit indicates said difference was less than zero, thereby forming N absolute values of said N differences, d) multiplying each of said N absolute values by itself, thereby forming N products, e) employing said arithmetic logic unit to add each of said N products to a corresponding one of N prior running sums, thereby forming N new running sums; until each of said plurality of pairs of first and second values are processed; 2) employing said arithmetic logic unit to add a final running sum of each of said N running sums, thereby forming a combined final running sum; and 3) dividing said combined final running sum for all of said plurality of pairs by said predetermined number.