Digital processor system with conditional carry and status function in arithmetic unit

Claim 1

An electronic digital processor system of the type implemented in a semiconductor LSI device, said system having a bit-parallel arithmetic unit with first and second inputs and an output, the arithmetic unit performing during a machine cycle arithmetic and logic operations on digits of numerical information applied to said inputs, one digit being produced at said output for each machine cycle, each digit having a plurality of parallel bits, memory means having input/output means and having a plurality of memory locations, addressing means associated with the memory means for selecting in response to command signals one of the plurality of memory locations for storing digits of numerical information in the memory means via the input/output means or recalling such information from the memory means via the input/output means, selector means coupled to the first and second inputs of the arithmetic unit for selecting in response to command signals any one of a plurality of different sources of digits of numerical information including said input/output means of the memory means and for applying such information to said inputs of the arithmetic unit, a carry output from the arithemtic unit and a carry input to the arithmetic unit, and logic means for applying a carry to the carry input in response to whether or not a carry was generated in the arithmetic unit at the carry output for the operation performed on the digits of numerical information by the arithmetic unit for either the digits applied to the inputs of the arithmetic unit during the current machine cycle or the digits applied to the inputs of the arithmetic unit during the previous machine cycle.