US5195052A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method for performing integer power operations
Assignee: International Business Machines Corp
•
Filing: 1991-12-13
•
Granted: 1993-03-16
•
Expires: 2011-12-13
Abstract
Abstract An arithmetic circuit for performing an integer power operation having a first register that is initially stored with integer power data, a second register stored with base data and a multiplier for multiplying the second register contents with a third register. A control circuit is provided for iteratively shifting the first register and for each iteration (1) selectively multiplying, according to data shifted from said first register, the second register data by the third register data and storing the results in the third register, and (2) multiplying the second register data by itself and storing the results back into the second register. These iterative steps are continued until the remaining data in the first register indicates that the arithmetic operation is complete, whereupon a completion signal is provided.
Inventors
- 👤 Faraydon O. Karim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/556; G06F2207/00; G06F2207/556; G06F2207/5561
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
118 words
An arithmetic circuit for performing an integer power operation comprising: first register means for storing exponent data; second register means for storing base data; multiplier means for multiplying data in said second register means and a third register means; and control means for iteratively shifting first register means data, and for each iteration, (1) selectively multiplying, according to data shifted from said first register means, said second register means data by said third register means data storing results in the third register means, and (2) multiplying said second register means data by itself storing results in said second register means, until remaining data in said first register means indicates arithmetic operation completion and providing a completion signal thereupon.
Claim 2
Dependent Claim
118 words
An arithmetic circuit for performing an integer power operation comprising: first register means for storing exponent data; second register means for storing base data; multiplier means for multiplying data in said second register means and a third register means; and control means for iteratively shifting first register means data, and for each iteration, (1) selectively multiplying, according to data shifted from said first register means, said second register means data by said third register means data storing results in the third register means, and (2) multiplying said second register means data by itself storing results in said second register means, until remaining data in said first register means indicates arithmetic operation completion and providing a completion signal thereupon.
Claim 3
Dependent Claim
24 words
An arithmetic circuit according to claim 1 wherein said control means further includes means for ORing the contents of the first register means data.
Claim 4
Dependent Claim
24 words
An arithmetic circuit according to claim 2 wherein said control means further includes a first latch to store the results from the ORing means.
Claim 5
Dependent Claim
29 words
An arithmetic circuit according to claim 3 wherein said control means further includes means to provide said completion signal when the contents of said first latch is a 0.
Claim 6
Dependent Claim
28 words
An arithmetic circuit according to claim 4 wherein said control means further includes a second latch to store data that has been shifted from said first register means.
Claim 7
Dependent Claim
19 words
An arithmetic circuit according to claim 5 wherein said multiplier means includes a results register for storing multiplication results.
Claim 8
Dependent Claim
30 words
An arithmetic circuit according to claim 6 wherein said multiplier means further includes a multiplexer connecting the results register and said second register to provide data to said third register.
Claim 9
Independent Claim
117 words
A method for performing an integer power operation in an arithmetic circuit having a first register, a second register, a multiplier circuit with a third register, said method comprising the steps of: (1) storing exponent data in said first register; (2) storing base data in said second register; (3) iteratively shifting first register data; (4) for each iteration, (A) selectively multiplying, according to data shifting from said first register, said second register data by said third register data storing results in the third register, and (B) multiplying said second register data by itself storing results in said second register; and (5) providing a completion signal when remaining data in said first register indicates integer power operation completion.
Claim 10
Independent Claim
117 words
A method for performing an integer power operation in an arithmetic circuit having a first register, a second register, a multiplier circuit with a third register, said method comprising the steps of: (1) storing exponent data in said first register; (2) storing base data in said second register; (3) iteratively shifting first register data; (4) for each iteration, (A) selectively multiplying, according to data shifting from said first register, said second register data by said third register data storing results in the third register, and (B) multiplying said second register data by itself storing results in said second register; and (5) providing a completion signal when remaining data in said first register indicates integer power operation completion.
Claim 11
Dependent Claim
18 words
A method according to claim 8 wherein step (1) further includes storing a 1 in the third register.
Claim 12
Dependent Claim
31 words
A method according to claim 9 wherein step (5) further includes ORing the remaining contents of the first register and providing the completion signal when the ORed results in a (0).
Claim 13
Dependent Claim
87 words
An arithmetic circuit for performing an integer power arithmetic operation comprising: first register means for storing exponent data; second register means for storing base data; multiplying means for multiplying said base data in said second register by a third register and maintaining an accumulative results in said third register; and control means for accumulating selective base data multiplications in said multiplying means according to data shifted from said first register means and providing a completion signal when the first register means data is in a null state.
Claim 14
Dependent Claim
87 words
An arithmetic circuit for performing an integer power arithmetic operation comprising: first register means for storing exponent data; second register means for storing base data; multiplying means for multiplying said base data in said second register by a third register and maintaining an accumulative results in said third register; and control means for accumulating selective base data multiplications in said multiplying means according to data shifted from said first register means and providing a completion signal when the first register means data is in a null state.
References Cited (Backward Citations)
US4225933A
Cited
US4229801A
Cited
US4410956A
Cited
SU1179327A1
Cited
SU1246092A1
Cited
US4758975A
Cited
US4787056A
Cited
SU1411740A1
Cited
DE3931545A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-15 | 1996-09-14 | 1997-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-15 | 2000-09-14 | 2001-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-15 | 2004-09-14 | 2005-03-16 | $7700.00 | Window Closed / Lapsed |