US5420059A
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Method of making a high performance MESFET with multiple quantum wells
Assignee: International Business Machines Corp
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Filing: 1994-02-18
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Granted: 1995-05-30
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Expires: 2014-02-18
Abstract
Abstract A superheterojunction Field Effect Transistor (FET) with a multi-region channel on a Silicon (Si) substrate. The FET is a Metal Semiconductor FET (MESFET) or, alternatively, a Junction FET (JFET). The multi-region channel has: A first region of Si extending from the FET's source to a point under the FET's gate, beyond the gate's midpoint; a second region extending from the first region to the FET's drain, comprised of a superlattice of alternating Si and SiGe layers; and, a third region of Si extending under the first two regions from the source to the drain. The first region has a laterally graded dopant that creates an accelerating electric field. The superlattice structure increases electron mobility and transit velocity.
Inventors
- 👤 S. Noor Mohammad
- 👤 Robert B. Renbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D30/832; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/87; H10D30/875; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; Y; Y10; Y10S; Y10S148/00; Y10S148/072; Y10S148/16
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
126 words
A method of fabricating a FET comprising the steps of: a. growing a layer of a first semiconductor material having a first conductivity type on a substrate; b. growing a superlattice structure above said substrate comprising the steps of: i) forming a trench in said first semiconductor material layer, ii) growing a first superlattice layer of a second semiconductor material in said trench, iii) growing a second superlattice layer of said first semiconductor material on said first superlattice layer, and, iv) repeating steps ii) and iii) to grow a plurality of said superlattice layers; c. doping a portion of said first semiconductor material layer; d. forming source and drain regions in said first semiconductor layer; and, e. forming a gate between said source and drain regions.
Claim 2
Independent Claim
126 words
A method of fabricating a FET comprising the steps of: a. growing a layer of a first semiconductor material having a first conductivity type on a substrate; b. growing a superlattice structure above said substrate comprising the steps of: i) forming a trench in said first semiconductor material layer, ii) growing a first superlattice layer of a second semiconductor material in said trench, iii) growing a second superlattice layer of said first semiconductor material on said first superlattice layer, and, iv) repeating steps ii) and iii) to grow a plurality of said superlattice layers; c. doping a portion of said first semiconductor material layer; d. forming source and drain regions in said first semiconductor layer; and, e. forming a gate between said source and drain regions.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein conductivity type of said first conductivity type is N type.
Claim 4
Dependent Claim
19 words
The method of claim 1 wherein said first semiconductor material is silicon and said second semiconductor material is SiGe.
Claim 5
Dependent Claim
11 words
The method of claim 3 wherein the mole fraction of Germanium≦0.5.
Claim 6
Dependent Claim
11 words
The method of claim 3 wherein the mole fraction of Germanium=0.5.
Claim 7
Dependent Claim
33 words
The method of claim 3 wherein said superlattice layers of said first material are between 300 Å and 1000 Å thick and said superlattice layers of said second material are 200 Å thick.
Claim 8
Dependent Claim
41 words
The method of claim 3 wherein said superlattice layers of said first material are undoped and said superlattice layers of said second material are doped with a N-type dopant density between 5*10 16 cm -3 and 10 17 cm -3 .
Claim 9
Dependent Claim
16 words
The method of claim 1 wherein said gate is metal and said FET is a MESFET.
Claim 10
Dependent Claim
17 words
The method of claim 1 wherein said gate is doped semiconductor and said FET is a JFET.
Claim 11
Independent Claim
159 words
A method of fabricating a FET comprising the steps of: a. growing a layer of a first semiconductor material having a first conductivity type on a substrate; b. growing a superlattice structure on said first semiconductor material layer comprising the steps of: i) growing a first superlattice layer of a second semiconductor material, ii) growing a second superlattice layer of said first semiconductor material on said first superlattice layer, and, iii) repeating steps i) and ii) to grow a plurality of said superlattice layers; c. forming a drain region, said drain region formed comprising the steps of: i) etching said grown superlattice layers to expose said layer of first semiconductor material, and ii) overgrowing said exposed layer of first semiconductor material until a top surface of said overgrown layer is co-planar with the top superlattice layer; d. forming a source-channel region; and, e. forming a gate between said drain region and a source region formed in said source-channel region.
Claim 12
Independent Claim
159 words
A method of fabricating a FET comprising the steps of: a. growing a layer of a first semiconductor material having a first conductivity type on a substrate; b. growing a superlattice structure on said first semiconductor material layer comprising the steps of: i) growing a first superlattice layer of a second semiconductor material, ii) growing a second superlattice layer of said first semiconductor material on said first superlattice layer, and, iii) repeating steps i) and ii) to grow a plurality of said superlattice layers; c. forming a drain region, said drain region formed comprising the steps of: i) etching said grown superlattice layers to expose said layer of first semiconductor material, and ii) overgrowing said exposed layer of first semiconductor material until a top surface of said overgrown layer is co-planar with the top superlattice layer; d. forming a source-channel region; and, e. forming a gate between said drain region and a source region formed in said source-channel region.
Claim 13
Dependent Claim
62 words
The method of claim 10 wherein the step (d) of forming the source-channel region comprises the steps of: i) etching in said superlattice an area for said source region, whereby said layer of first semiconductor material is exposed; and ii) overgrowing said layer of first semiconductor material until a top surface of said overgrown layer is co-planar with the top superlattice layer.
Claim 14
Dependent Claim
19 words
The method of claim 10 wherein said first semiconductor material is silicon and said second semiconductor material is SiGe.
Claim 15
Dependent Claim
11 words
The method of claim 12 wherein the mole fraction of Germanium≦0.5.
Claim 16
Dependent Claim
11 words
The method of claim 12 wherein the mole fraction of Germanium=0.5.
Claim 17
Dependent Claim
33 words
The method of claim 12 wherein said superlattice layers of said first material are between 300 Å and 1000 Å thick and said superlattice layers of said second material are 200 Å thick.
Claim 18
Dependent Claim
41 words
The method of claim 12 wherein said superlattice layers of said first material are undoped and said superlattice layers of said second material are doped with a N-type dopant density between 5*10 16 cm -3 and 10 17 cm -3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |