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Junction contact process and structure for semiconductor technologies

Assignee: Texas Instruments Inc
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Filing: 1994-01-14
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Granted: 1995-05-30
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Expires: 2014-01-14
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Abstract

Abstract A device and method for forming an improved junction contact in a semiconductor device (10). A portion of an interlevel dielectric layer (28) is etched away to expose a surface of at least one junction region (26). Next, a dielectric layer is formed over the exposed surface of the junction regions (26). The semiconductor device (10) is then annealed in a nitrogen-containing ambient to diffuse a portion (34) of the at least one junction region (26) further into a substrate (12). The dielectric layer may then be removed and contact plugs (36) formed in the exposed area. Finally, a metal interconnect layer (38) may be formed to connect to the junction regions (26) through the contact plugs (36).

Inventors

  • 👤 Mehrdad M. Moslehi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 04:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10P; H10P14/00; H10P14/40; H10P14/42; Y; Y10; Y10S; Y10S438/00; Y10S438/965

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 83 words
A method for forming an improved junction contact in a semiconductor device, comprising the steps of: a. etching at least one contact hole through an interlevel dielectric layer to expose a portion of at least one junction region; b. forming a dielectric layer over said portion of said at least one junction region; and c. annealing said semiconductor device in a nitrogen-containing ambient to diffuse said portion of said at least one junction region with said overlying dielectric layer further into a substrate.
Claim 2
Independent Claim 83 words
A method for forming an improved junction contact in a semiconductor device, comprising the steps of: a. etching at least one contact hole through an interlevel dielectric layer to expose a portion of at least one junction region; b. forming a dielectric layer over said portion of said at least one junction region; and c. annealing said semiconductor device in a nitrogen-containing ambient to diffuse said portion of said at least one junction region with said overlying dielectric layer further into a substrate.
Claim 3
Dependent Claim 11 words
The method of claim 1, wherein said nitrogen-containing ambient comprises ammonia.
Claim 4
Dependent Claim 18 words
The method of claim 1, wherein said annealing step is performed at a temperature less than 850° C.
Claim 5
Dependent Claim 24 words
The method of claim 1, wherein said annealing step is performed at a pressure in the range of below atmospheric pressure to 100 atmospheres.
Claim 6
Dependent Claim 22 words
The method of claim 1, wherein said annealing step is performed at a pressure in the range of 20 to 100 atmospheres.
Claim 7
Dependent Claim 17 words
The method of claim 1, wherein said dielectric layer has a thickness in the range of 50Å-1000Å.
Claim 8
Dependent Claim 17 words
The method of claim 1, wherein said dielectric layer has a thickness in the range of 100-Å200Å.
Claim 9
Dependent Claim 17 words
The method of claim 1, wherein said step of forming said dielectric layer comprises low-pressure chemical-vapor deposition.
Claim 10
Dependent Claim 24 words
The method of claim 1, wherein said step of forming said dielectric layer comprises thermally growing said dielectric layer using a thermal oxidation process.
Claim 11
Dependent Claim 51 words
The method of claim 1 further comprising the steps of: a. removing said dielectric layer; b. forming a contact plug in said at least one contact hole; and c. forming a metal interconnect layer, wherein said contact plug electrically connects said at least one junction region to said metal interconnect layer.
Claim 12
Dependent Claim 19 words
The method of claim 1, wherein said at least one junction region comprises a plurality of source/drain junction regions.
Claim 13
Dependent Claim 14 words
The method of claim 1, wherein said dielectric layer is a silicon dioxide layer.
Claim 14
Independent Claim 145 words
A method of forming a semiconductor device, comprising the steps of: a. forming a plurality of transistors at the surface of a semiconductor body, each of said transistors having a source region, a drain region, and a gate; b. forming an interlevel dielectric layer over said plurality of transistors and said semiconductor body; c. etching a plurality of contact holes through said interlevel dielectric layer over said source and drain regions; d. forming a dielectric layer in said contact holes over said source and drain regions; e. annealing said semiconductor device in a nitrogen-containing atmosphere to extend a portion of each of said source and drain regions with said overlying dielectirc layer further into said semiconductor body; f. removing said dielectric layer; g. filling said contact holes with conductive plugs; and h. forming an interconnect layer adjacent said interlevel dielectric layer and said conductive plugs.
Claim 15
Independent Claim 145 words
A method of forming a semiconductor device, comprising the steps of: a. forming a plurality of transistors at the surface of a semiconductor body, each of said transistors having a source region, a drain region, and a gate; b. forming an interlevel dielectric layer over said plurality of transistors and said semiconductor body; c. etching a plurality of contact holes through said interlevel dielectric layer over said source and drain regions; d. forming a dielectric layer in said contact holes over said source and drain regions; e. annealing said semiconductor device in a nitrogen-containing atmosphere to extend a portion of each of said source and drain regions with said overlying dielectirc layer further into said semiconductor body; f. removing said dielectric layer; g. filling said contact holes with conductive plugs; and h. forming an interconnect layer adjacent said interlevel dielectric layer and said conductive plugs.
Claim 16
Dependent Claim 11 words
The method of claim 13, wherein said nitrogen-containing ambient comprises ammonia.
Claim 17
Dependent Claim 32 words
The method of claim 13, wherein said annealing step is performed at a temperature less than 850° C. and at a pressure in the range of below atmospheric pressure to 100 atmospheres.
Claim 18
Dependent Claim 22 words
The method of claim 13, wherein said annealing step is performed at a pressure in the range of 20 to 100 atmospheres.
Claim 19
Dependent Claim 17 words
The method of claim 13, wherein said dielectric layer has a thickness in the range of 100Å-200Å.
Claim 20
Dependent Claim 17 words
The method of claim 13, wherein said step of forming said dielectric layer comprises low-pressure chemical-vapor deposition.
Claim 21
Dependent Claim 19 words
The method of claim 13, wherein said step of forming said dielectric layer comprises thermally growing said dielectric layer.
Claim 22
Dependent Claim 26 words
The method of claim 1, wherein said annealing step diffuses said portion of said at least one junction further into the substrate in a self-aligned manner.
Claim 23
Dependent Claim 28 words
The method of claim 13, wherein said annealing step diffuses said portion of each of said source and drain regions further into the substrate in a selfaligned manner.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-05-29 1998-11-28 1999-05-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-05-29 2002-11-28 2003-05-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-05-29 2006-11-28 2007-05-30 $7700.00 Window Closed / Lapsed

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