Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit

Claim 2

A data bus control circuit for a semiconductor integrated circuit, said semiconductor integrated circuit having input/output terminals for data exchange with a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit, comprising: a bi-directional bus buffer for connecting a data bus which is connected to said CPU with said input/output terminals, said bi-directional bus buffer including first and second buffer circuits provided for each of respective signal lines of said data bus, said first and second buffer circuits being connected between a corresponding signal line of said data bus and a corresponding input/output terminal, an input terminal of said first buffer circuit being connected to said corresponding input/output terminal and an output terminal of said first buffer circuit being connected to said corresponding signal line, an input terminal of said second buffer circuit being connected to said corresponding signal line and output terminal of said second buffer circuit being connected to said corresponding input/output terminal, said first buffer circuit becoming conductive when a high level signal is applied to a control terminal thereof and said second buffer circuit becoming conductive when a low level signal is applied to a control terminal thereof, and an electronic circuit for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted frown said CPU and executing the switching of a signal propagation direction of said bi-directional bus buffer with a predetermined time delay after said read signal is output from said CPU in order to prevent a collision between a signal output by said CPU and a signal output by said external device on said data bus, said electronic circuit including: a flip-flop circuit supplied with said read signal at a data input terminal thereof and a clock signal at a clock input terminal thereof, and an AND circuit supplied with said read signal at one terminal thereof, another input terminal of said AND circuit being connected to a data output terminal of said flip-flop circuit, and an output terminal of said AND circuit being connected to said control terminals of said first and second buffer circuits.

Claim 3

A data bus control circuit for a semiconductor integrated circuit, said semiconductor integrated circuit having input/output terminals for data exchange with a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit, comprising: a bi-directional bus buffer for connecting a data bus connected to said CPU with said input/output terminals, said bi-directional bus buffer including first and second buffer circuits provided for each of respective signal lines of said data bus, said first and second buffer circuits being connected between a corresponding signal line of said data bus and a corresponding input/output terminal, an input terminal of said first buffer circuit being connected to said corresponding input/output terminal and an output terminal of said first buffer circuit being connected to said corresponding signal line, an input terminal of said second buffer circuit being connected to said corresponding signal line and output terminal of said second buffer circuit being connected to said corresponding input/output terminal, said first buffer circuit becoming conductive when a high level signal is applied to a control terminal thereof and said second buffer circuit becoming conductive when a low level signal is applied to a control terminal thereof, and an electronic circuit for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted from said CPU and executing the switching of a signal propagation direction of said bi-directional bus buffer with a predetermined time delay after said read signal is output from said CPU in order to prevent a collision between a signal output by said CPU and a signal output by said external device on said data bus, said electronic circuit including: a delay circuit supplied with said read signal at an input terminal thereof, and an AND circuit supplied with said read signal at one input terminal thereof, the other input terminal of said AND circuit being connected to an output terminal of said delay circuit, an output terminal of said AND circuit being connected to said control terminals of said first and second buffer circuits.

Claim 4

A data bus control circuit for a semiconductor integrated circuit, said semiconductor integrated circuit having input/output terminals for data exchange with a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit, comprising: a bi-directional bus buffer for connecting a data bus connected to said CPU with said input/output terminals, said bi-directional bus buffer including first and second buffer circuits provided for each of respective signal lines of said data bus, said first and second buffer circuits being connected between a corresponding signal line of said data bus and a corresponding input/output terminal, an input terminal of said first buffer circuit being connected to said corresponding input/output terminal and an output terminal of said first buffer circuit being connected to said corresponding signal line, an input terminal of said second buffer circuit being connected to said corresponding signal line and output terminal of said second buffer circuit being connected to said corresponding input/output terminal, said first buffer circuit becoming conductive when a high level signal is applied to a control terminal thereof and said second buffer circuit becoming conductive when a low level signal is applied to a control terminal thereof, and an electronic circuit for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted from said CPU and executing the switching of a signal propagation direction of said bi-directional bus buffer with a predetermined time delay after said read signal is output from said CPU in order to prevent a collision between a signal output by said CPU and a signal output by said external device on said data bus, said electronic circuit including: a delay circuit supplied with said read signal at an input terminal thereof, and an AND circuit supplied with said read signal at one input terminal thereof, the other input terminal of said AND circuit being connected to an output terminal of said delay circuit, an output terminal of said AND circuit being connected to said control terminals of said first and second buffer circuits.

Claim 5

A data bus control circuit for a semiconductor integrated circuit, said semiconductor integrated circuit having input/output terminals for data exchange with a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit, comprising: a bi-directional bus buffer for connecting a data bus which is connected to said CPU with said input/output terminals, said bi-directional bus buffer including first and second buffer circuits provided for each of respective signal lines of said data bus, said first and second buffer circuits being connected between a corresponding signal line of said data bus and a corresponding input/output terminal, an input terminal of said first buffer circuit being connected to said corresponding input/output terminal and an output terminal of said first buffer circuit being connected to said corresponding signal line, an input terminal of said second buffer circuit being connected to said corresponding signal line and output terminal of said second buffer circuit being connected to said corresponding input/output terminal, said first buffer circuit becoming conductive when a high level signal is applied to a control terminal thereof and said second buffer circuit becoming conductive when a low level signal is applied to a control terminal thereof, and an electronic circuit for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted from said CPU and executing switching of a signal propagation direction of said bi-directional bus buffer with a predetermined time delay after said read signal is output from said CPU in order to prevent a collision between a signal output by said CPU and a signal output by said external device on said data bus, said electronic circuit including: a flip-flop circuit supplied with said read signal at a data input terminal thereof and supplied with a clock signal at a clock input terminal thereof, a first AND circuit supplied with said read signal at one terminal thereof, another input terminal of said first AND circuit being connected to a data output terminal of said flip-flop circuit, a second AND circuit supplied with a output signal of said first AND circuit at one terminal thereof, the other input terminal of said second AND circuit being connected to a data bus release signal terminal of said CPU, an output terminal of said second AND circuit being connected to said control terminal of said first buffer circuit, an inverter supplied with a data bus release signal at an input terminal, and an OR circuit supplied with said output signal of said first AND circuit at one terminal thereof, another terminal of said OR circuit being connected to an output terminal of said inverter, an output terminal of said OR circuit being connected to said control terminal of said second buffer circuit.

Claim 6

A data bus control circuit for a semiconductor integrated circuit, said semiconductor integrated circuit having input/output terminals for data exchange with a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit, comprising: a bi-directional bus buffer for connecting a data bus which is connected to said CPU with said input/output terminals, said bi-directional bus buffer including first and second buffer circuits provided for each of respective signal lines of said data bus, said first and second buffer circuits being connected between a corresponding signal line of said data bus and a corresponding input/output terminal, an input terminal of said first buffer circuit being connected to said corresponding input/output terminal and an output terminal of said first buffer circuit being connected to said corresponding signal line, an input terminal of said second buffer circuit being connected to said corresponding signal line and output terminal of said second buffer circuit being connected to said corresponding input/output terminal, said first buffer circuit becoming conductive when a high level signal is applied to a control terminal thereof and said second buffer circuit becoming conductive when a low level signal is applied to a control terminal thereof, and an electronic circuit for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted from said CPU and executing switching of a signal propagation direction of said bi-directional bus buffer with a predetermined time delay after said read signal is output from said CPU in order to prevent a collision between a signal output by said CPU and a signal output by said external device on said data bus, said electronic circuit including: a flip-flop circuit supplied with said read signal at a data input terminal thereof and supplied with a clock signal at a clock input terminal thereof, a first AND circuit supplied with said read signal at one terminal thereof, another input terminal of said first AND circuit being connected to a data output terminal of said flip-flop circuit, a second AND circuit supplied with a output signal of said first AND circuit at one terminal thereof, the other input terminal of said second AND circuit being connected to a data bus release signal terminal of said CPU, an output terminal of said second AND circuit being connected to said control terminal of said first buffer circuit, an inverter supplied with a data bus release signal at an input terminal, and an OR circuit supplied with said output signal of said first AND circuit at one terminal thereof, another terminal of said OR circuit being connected to an output terminal of said inverter, an output terminal of said OR circuit being connected to said control terminal of said second buffer circuit.