Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments

Claim 1

A general purpose parallel digital processor including a plurality of processing modules coupled to a common main memory, the improvement comprising: parallel processing modules (PPM's) each including, a program register for storing instruction code; at least two data registers for storing data to be processed; a separate parallel port for each of said registers to permit simultaneous transfer of data and code to said respective registers from the common main memory; an arithmetic logic unit (ALU) coupled to receive data from said data registers; an instruction decoder responsive to said instruction code stored in said program register, and operative to control said ALU to process data from said data registers according to instructions from said program register; said main memory being organized in columns and rows with a separate column of memory being associated with each of said ports of said PPMs to permit transfer of the data from the associated columns to said register via said ports; and said digital parallel processor further including a plurality of lateral transfer buses with interrupt switches for selectively interrupting the transfer bus to form a plurality of segments, and electronic switches for selectively connecting each of said segments to at least one of said columns of memory and associate port.