Patent US5418930A successfully refreshed from Google Patents.
US5418930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for interfacing asynchronous to synchronous communications
Assignee: International Business Machines Corp
•
Filing: 1991-09-05
•
Granted: 1995-05-23
•
Expires: 2011-09-05
Abstract
Abstract An Asynchronous Communications Interface to Synchronous Circuit having three stages is disclosed. The first stage captures the control and data signals from an asynchronous bus and converts them into signals which are synchronous to the internal clocks of the interface chip. The second stage of the interface is a synchronous state machine which utilizes the synchronized signals generated by the first stage to determine the current state of the asynchronous bus. The third stage of the interface uses the data generated by the synchronous state machine and the control and data signal capture logic to validate the data in a synchronous manner. This allows further processing of the data from the asynchronous bus without the use of any further asynchronous logic or timing.
Inventors
- 👤 Jeffery L. Swarts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F11/00; G06F11/22; G06F11/2205; G06F11/221
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A circuit for capturing and validating data from an asynchronous micro channel bus in accordance with micro channel protocol and data transfer modes consistent with LSSD guidelines for use on a synchronous chip, said circuit comprising: means responsive to an asynchronous data valid signal and at least two internal clock signals for converting the asynchronous data valid signal to a synchronous data valid signal; means responsive to an asynchronous streaming data signal and at least two internal clock signals for converting the asynchronous streaming data signal to a synchronous streaming data signal; means responsive to an asynchronous data signal, the asynchronous streaming data signal, the asynchronous data valid signal and the two internal clock signals for converting the asynchronous data signal to an asynchronously latched data signal; means for asynchronously latching an asynchronous address signal using the asynchronous data valid signal as a clock signal to a first latch and the asynchronous streaming data signal as a clock signal to a second latch; a state machine which uses the synchronous data valid signal and the asynchronous streaming data signal to generate a plurality of synchronous signals representative of a current state of the asynchronous bus; means responsive to at least one of the synchronous signals generated by the state machine for validating the asynchronously latched data signal in a synchronous manner; and means for validating the asynchronously latched address signal using at least one of the synchronous signals representative of the current state of the asynchronous bus.
Claim 2
Dependent Claim
247 words
A circuit for capturing and validating data from an asynchronous micro channel bus in accordance with micro channel protocol and data transfer modes consistent with LSSD guidelines for use on a synchronous chip, said circuit comprising: means responsive to an asynchronous data valid signal and at least two internal clock signals for converting the asynchronous data valid signal to a synchronous data valid signal; means responsive to an asynchronous streaming data signal and at least two internal clock signals for converting the asynchronous streaming data signal to a synchronous streaming data signal; means responsive to an asynchronous data signal, the asynchronous streaming data signal, the asynchronous data valid signal and the two internal clock signals for converting the asynchronous data signal to an asynchronously latched data signal; means for asynchronously latching an asynchronous address signal using the asynchronous data valid signal as a clock signal to a first latch and the asynchronous streaming data signal as a clock signal to a second latch; a state machine which uses the synchronous data valid signal and the asynchronous streaming data signal to generate a plurality of synchronous signals representative of a current state of the asynchronous bus; means responsive to at least one of the synchronous signals generated by the state machine for validating the asynchronously latched data signal in a synchronous manner; and means for validating the asynchronously latched address signal using at least one of the synchronous signals representative of the current state of the asynchronous bus.
Claim 3
Dependent Claim
72 words
The circuit as recited in claim 1 which further comprises: means responsive to an asynchronous address signal, the asynchronous data valid signal, the asynchronous streaming data signal and at least two internal clock signals for converting the asynchronous address signal to an asynchronously latched address signal; and, wherein the validating means also uses the synchronous signals generated by the state machine for validating the asynchronously latched address signal in a synchronous manner.
Claim 4
Dependent Claim
89 words
The circuit as recited in claim 2 which further comprises: means responsive to an asynchronous ready slave signal, the asynchronous data valid signal, the asynchronous streaming data signal and at least two internal clock signals for generating an asynchronously latched ready slave signal and a synchronous ready slave signal; and, where the state machine also uses the synchronous ready slave signal to generate the plurality of synchronous signals representative of the current state of the asynchronous bus, and the synchronous data and synchronous address signals in a synchronous manner.
Claim 5
Dependent Claim
27 words
The circuit as recited in claim 1 wherein signals generated by the state machine can be used for data and address signal validation throughout the synchronous chip.
Claim 6
Independent Claim
230 words
A method for capturing and validating data from an asynchronous micro channel bus in accordance with micro channel protocols and data transfer modes consistent with LSSD guidelines for use on a synchronous chip, said method comprising the steps of: converting an asynchronous data valid signal to a synchronous data valid signal with at least two successive internal clock signals; converting an asynchronous streaming data signal to a synchronous streaming data signal with at least two successive internal clock signals; asynchronously latching an asynchronous data signal using the asynchronous data valid signal and the asynchronous streaming data signals using the asynchronous data valid signal or the asynchronous streaming data signal as a clock signal; asynchronously latching an asynchronous address signal using the asynchronous data valid signal as a clock signal to a first latch and the asynchronous streaming data signal as a clock signal to a second latch; generating a plurality of synchronous signals representative, each signal representative of a current state of the asynchronous bus using the synchronous data valid signal and streaming data signal as an input bus; validating the asynchronous latched data signal using at least one of the synchronous signals representative of the current state of the asynchronous bus in a synchronous manner; and validating the asynchronously latched address signal using at least one of the synchronous signals representative of the current state of the asynchronous bus.
Claim 7
Independent Claim
230 words
A method for capturing and validating data from an asynchronous micro channel bus in accordance with micro channel protocols and data transfer modes consistent with LSSD guidelines for use on a synchronous chip, said method comprising the steps of: converting an asynchronous data valid signal to a synchronous data valid signal with at least two successive internal clock signals; converting an asynchronous streaming data signal to a synchronous streaming data signal with at least two successive internal clock signals; asynchronously latching an asynchronous data signal using the asynchronous data valid signal and the asynchronous streaming data signals using the asynchronous data valid signal or the asynchronous streaming data signal as a clock signal; asynchronously latching an asynchronous address signal using the asynchronous data valid signal as a clock signal to a first latch and the asynchronous streaming data signal as a clock signal to a second latch; generating a plurality of synchronous signals representative, each signal representative of a current state of the asynchronous bus using the synchronous data valid signal and streaming data signal as an input bus; validating the asynchronous latched data signal using at least one of the synchronous signals representative of the current state of the asynchronous bus in a synchronous manner; and validating the asynchronously latched address signal using at least one of the synchronous signals representative of the current state of the asynchronous bus.
References Cited (Backward Citations)
US4435759A
Cited
US4627070A
Cited
US4631666A
Cited
US4593282A
Cited
US4665518A
Cited
US4805194A
Cited
US4737971A
Cited
US4962474A
Cited
US4992930A
Cited
GB2235995A
Cited
US5220651A
Cited
US5191657A
Cited
US5054020A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-22 | 1998-11-21 | 1999-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-22 | 2002-11-21 | 2003-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-22 | 2006-11-21 | 2007-05-23 | $7700.00 | Window Closed / Lapsed |