US5416362A
Expired / Lapsed
US
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Transparent flip-flop
Assignee: Unisys Corp
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Filing: 1993-09-10
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Granted: 1995-05-16
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Expires: 2013-09-10
Abstract
Abstract An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.
Inventors
- 👤 Larry L. Byers
- 👤 Fernando W. Arraut
- 👤 Dale K. Seppa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:53
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
986 words
Transparent bistable storage apparatus comprising: a. a master latch having a SET input port, a CLEAR input port, a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state; b. a slave latch having a SET input port, a CLEAR input port, a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state and wherein said DATA input port of said slave latch is coupled to said Q output port of said master latch; c. a PSET input pin coupled to said SET input port of said master latch and to said SET input port of said slave latch for placing a logic-1 in said master latch and said slave latch when said PSET input pin contains a signal having a predefined logic level; d. a CLEAR input pin coupled to said CLR input port of said master latch and to said CLR input port of said slave latch for placing a logic-0 in said master latch and said slave latch when said CLEAR input pin contains a signal having a predefined logic level; e. a first NOR gate having input ports NOR1, NOR2, NOR3, and NOR4 and output port NOROUT wherein said NOROUT output port of said first NOR gate is coupled to said DATA input port of said master latch; f. a first AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said first AND gate is coupled to a SDI input pin and said AND2 input port of said first AND gate is coupled to a SCAN input pin and wherein said ANDOUT output port of said first AND gate is coupled to said NOR1 input port of said first NOR gate; g. a first inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said first inverter is coupled to said SCAN input pin; h. a second AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said second AND gate is coupled to a EN1 input pin and said AND2 input port of said second AND gate is coupled to a EN2 input pin; i. a second inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said second inverter is coupled to said ANDOUT output port of said second AND gate; j. a third AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said third AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said third AND gate is coupled to said ANDOUT output port of said second AND gate and said AND3 input port of said third AND gate is coupled to a D input pin and wherein said ANDOUT output port of said third AND gate is coupled to said NOR2 input port of said first NOR gate; k. a fourth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fourth AND gate is coupled to said D input pin and said AND2 input port of said fourth AND gate is coupled to said INVOUT output port of said first inverter and said AND3 input port of said fourth AND gate is coupled to a transparent enable pin and wherein said ANDOUT output port of said fourth AND gate is coupled to said NOR3 input port of said first NOR gate; l. a fifth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fifth AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said fifth AND gate is coupled to said INVOUT output port of said second inverter and said AND3 input port of said fifth AND gate is coupled to said Q output port of said slave latch and wherein said ANDOUT output port of said fifth AND gate is coupled to said NOR4 input port of said first NOR gate; m. a first NAND gate having input ports NAND1, NAND2, and output port NANDOUT wherein said NAND1 input port of said first NAND gate is coupled to said INVOUT of said first inverter and said NAND2 input port of said first NAND gate is coupled to said transparent enable pin; n. a sixth AND gate having input ports AND1, AND2, and output port ANDOUT wherein said AND1 input port of said sixth AND gate is coupled to said NANDOUT output port of said first NAND gate and said AND2 input port of said sixth AND gate is coupled to a CLK input pin and wherein said ANDOUT output port of said sixth AND gate is coupled to said CLOCK input port of said master latch; o. a third inverter having an INV1 input port and an INVOUT output port wherein said INV1 input port of said third inverter is coupled to said NANDOUT output port of said first NAND gate; and p. a second NOR gate having input ports NOR1, NOR2, and output port NOROUT wherein said NOR1 input port of said second NOR gate is coupled to said ANDOUT output port of said sixth AND gate and said NOR2 input port of said second NOR gate is coupled to said INVOUT output port of said third inverter and wherein said NOROUT of said second NOR gate is coupled to said CLOCK input port of said slave latch.
Claim 2
Dependent Claim
986 words
Transparent bistable storage apparatus comprising: a. a master latch having a SET input port, a CLEAR input port, a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state; b. a slave latch having a SET input port, a CLEAR input port, a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state and wherein said DATA input port of said slave latch is coupled to said Q output port of said master latch; c. a PSET input pin coupled to said SET input port of said master latch and to said SET input port of said slave latch for placing a logic-1 in said master latch and said slave latch when said PSET input pin contains a signal having a predefined logic level; d. a CLEAR input pin coupled to said CLR input port of said master latch and to said CLR input port of said slave latch for placing a logic-0 in said master latch and said slave latch when said CLEAR input pin contains a signal having a predefined logic level; e. a first NOR gate having input ports NOR1, NOR2, NOR3, and NOR4 and output port NOROUT wherein said NOROUT output port of said first NOR gate is coupled to said DATA input port of said master latch; f. a first AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said first AND gate is coupled to a SDI input pin and said AND2 input port of said first AND gate is coupled to a SCAN input pin and wherein said ANDOUT output port of said first AND gate is coupled to said NOR1 input port of said first NOR gate; g. a first inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said first inverter is coupled to said SCAN input pin; h. a second AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said second AND gate is coupled to a EN1 input pin and said AND2 input port of said second AND gate is coupled to a EN2 input pin; i. a second inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said second inverter is coupled to said ANDOUT output port of said second AND gate; j. a third AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said third AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said third AND gate is coupled to said ANDOUT output port of said second AND gate and said AND3 input port of said third AND gate is coupled to a D input pin and wherein said ANDOUT output port of said third AND gate is coupled to said NOR2 input port of said first NOR gate; k. a fourth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fourth AND gate is coupled to said D input pin and said AND2 input port of said fourth AND gate is coupled to said INVOUT output port of said first inverter and said AND3 input port of said fourth AND gate is coupled to a transparent enable pin and wherein said ANDOUT output port of said fourth AND gate is coupled to said NOR3 input port of said first NOR gate; l. a fifth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fifth AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said fifth AND gate is coupled to said INVOUT output port of said second inverter and said AND3 input port of said fifth AND gate is coupled to said Q output port of said slave latch and wherein said ANDOUT output port of said fifth AND gate is coupled to said NOR4 input port of said first NOR gate; m. a first NAND gate having input ports NAND1, NAND2, and output port NANDOUT wherein said NAND1 input port of said first NAND gate is coupled to said INVOUT of said first inverter and said NAND2 input port of said first NAND gate is coupled to said transparent enable pin; n. a sixth AND gate having input ports AND1, AND2, and output port ANDOUT wherein said AND1 input port of said sixth AND gate is coupled to said NANDOUT output port of said first NAND gate and said AND2 input port of said sixth AND gate is coupled to a CLK input pin and wherein said ANDOUT output port of said sixth AND gate is coupled to said CLOCK input port of said master latch; o. a third inverter having an INV1 input port and an INVOUT output port wherein said INV1 input port of said third inverter is coupled to said NANDOUT output port of said first NAND gate; and p. a second NOR gate having input ports NOR1, NOR2, and output port NOROUT wherein said NOR1 input port of said second NOR gate is coupled to said ANDOUT output port of said sixth AND gate and said NOR2 input port of said second NOR gate is coupled to said INVOUT output port of said third inverter and wherein said NOROUT of said second NOR gate is coupled to said CLOCK input port of said slave latch.
Claim 3
Dependent Claim
869 words
Transparent bistable storage apparatus comprising: a. a master latch having a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state; b. a slave latch having a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when-said CLOCK input port is in the complement of said predefined state and wherein said DATA input port of said slave latch is coupled to said Q output port of said master latch; c. a first NOR gate having input ports NOR1, NOR2, NOR3, and NOR4 and output port NOROUT wherein said NOROUT output port of said first NOR gate is coupled to said DATA input port of said master latch; d. a first AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said first AND gate is coupled to a SDI input pin and said AND2 input port of said first AND gate is coupled to a SCAN input pin and wherein said ANDOUT output port of said first AND gate is coupled to said NOR1 input port of said first NOR gate; e. a first inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said first inverter is coupled to said SCAN input pin; f. a second AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said second AND gate is coupled to a EN1 input pin and said AND2 input port of said second AND gate is coupled to a EN2 input pin; g. a second inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said second inverter is coupled to said ANDOUT output port of said second AND gate; h. a third AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said third AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said third AND gate is coupled to said ANDOUT output port of said second AND gate and said AND3 input port of said third AND gate is coupled to a D input pin and wherein said ANDOUT output port of said third AND gate is coupled to said NOR2 input port of said first NOR gate; i. a fourth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fourth AND gate is coupled to said D input pin and said AND2 input port of said fourth AND gate is coupled to said INVOUT output port of said first inverter and said AND3 input port of said fourth AND gate is coupled to a transparent enable pin and wherein said ANDOUT output port of said fourth AND gate is coupled to said NOR3 input port of said first NOR gate; j. a fifth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fifth AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said fifth AND gate is coupled to said INVOUT output port of said second inverter and said AND3 input port of said fifth AND gate is coupled to said Q output port of said slave latch and wherein said ANDOUT output port of said fifth AND gate is coupled to said NOR4 input port of said first NOR gate; k. a first NAND gate having input ports NAND1, NAND2, and output port NANDOUT wherein said NAND1 input port of said first NAND gate is coupled to said INVOUT of said first inverter and said NAND2 input port of said first NAND gate is coupled to said transparent enable pin; l. a sixth AND gate having input ports AND1, AND2, and output port ANDOUT wherein said AND1 input port of said sixth AND gate is coupled to said NANDOUT output port of said first NAND gate and said AND2 input port of said sixth AND gate is coupled to a CLK input pin and wherein said ANDOUT output port of said sixth AND gate is coupled to said CLOCK input port of said master latch; m. a third inverter having an INV1 input port and an INVOUT output port wherein said INV1 input port of said third inverter is coupled to said NANDOUT output port of said first NAND gate; and n. a second NOR gate having input ports NOR1, NOR2, and output port NOROUT wherein said NOR1 input port of said second NOR gate is coupled to said ANDOUT output port of said sixth AND gate and said NOR2 input port of said second NOR gate is coupled to said INVOUT output port of said third inverter and wherein said NOROUT of said second NOR gate is coupled to said CLOCK input port of said slave latch.
Claim 4
Dependent Claim
869 words
Transparent bistable storage apparatus comprising: a. a master latch having a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when said CLOCK input port is in the complement of said predefined state; b. a slave latch having a DATA input port, a CLOCK input port, and a Q output port for latching data when said CLOCK input port is in a predefined state and for becoming transparent when-said CLOCK input port is in the complement of said predefined state and wherein said DATA input port of said slave latch is coupled to said Q output port of said master latch; c. a first NOR gate having input ports NOR1, NOR2, NOR3, and NOR4 and output port NOROUT wherein said NOROUT output port of said first NOR gate is coupled to said DATA input port of said master latch; d. a first AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said first AND gate is coupled to a SDI input pin and said AND2 input port of said first AND gate is coupled to a SCAN input pin and wherein said ANDOUT output port of said first AND gate is coupled to said NOR1 input port of said first NOR gate; e. a first inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said first inverter is coupled to said SCAN input pin; f. a second AND gate having input ports AND1, AND2 and output port ANDOUT wherein said AND1 input port of said second AND gate is coupled to a EN1 input pin and said AND2 input port of said second AND gate is coupled to a EN2 input pin; g. a second inverter having an INV1 input port and a INVOUT output port wherein said INV1 input port of said second inverter is coupled to said ANDOUT output port of said second AND gate; h. a third AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said third AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said third AND gate is coupled to said ANDOUT output port of said second AND gate and said AND3 input port of said third AND gate is coupled to a D input pin and wherein said ANDOUT output port of said third AND gate is coupled to said NOR2 input port of said first NOR gate; i. a fourth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fourth AND gate is coupled to said D input pin and said AND2 input port of said fourth AND gate is coupled to said INVOUT output port of said first inverter and said AND3 input port of said fourth AND gate is coupled to a transparent enable pin and wherein said ANDOUT output port of said fourth AND gate is coupled to said NOR3 input port of said first NOR gate; j. a fifth AND gate having input ports AND1, AND2, AND3 and output port ANDOUT wherein said AND1 input port of said fifth AND gate is coupled to said INVOUT of said first inverter and said AND2 input port of said fifth AND gate is coupled to said INVOUT output port of said second inverter and said AND3 input port of said fifth AND gate is coupled to said Q output port of said slave latch and wherein said ANDOUT output port of said fifth AND gate is coupled to said NOR4 input port of said first NOR gate; k. a first NAND gate having input ports NAND1, NAND2, and output port NANDOUT wherein said NAND1 input port of said first NAND gate is coupled to said INVOUT of said first inverter and said NAND2 input port of said first NAND gate is coupled to said transparent enable pin; l. a sixth AND gate having input ports AND1, AND2, and output port ANDOUT wherein said AND1 input port of said sixth AND gate is coupled to said NANDOUT output port of said first NAND gate and said AND2 input port of said sixth AND gate is coupled to a CLK input pin and wherein said ANDOUT output port of said sixth AND gate is coupled to said CLOCK input port of said master latch; m. a third inverter having an INV1 input port and an INVOUT output port wherein said INV1 input port of said third inverter is coupled to said NANDOUT output port of said first NAND gate; and n. a second NOR gate having input ports NOR1, NOR2, and output port NOROUT wherein said NOR1 input port of said second NOR gate is coupled to said ANDOUT output port of said sixth AND gate and said NOR2 input port of said second NOR gate is coupled to said INVOUT output port of said third inverter and wherein said NOROUT of said second NOR gate is coupled to said CLOCK input port of said slave latch.
Claim 5
Dependent Claim
52 words
Transparent bistable storage apparatus according to claim 1 wherein said apparatus being further operative such that when a selected signal appears at said transparency enable pin data appearing at said D input pin will pass directly through said at least one latch storage device to said at least one Q output port.
Claim 6
Dependent Claim
43 words
Transparent bistable storage apparatus according to claim 1 wherein said apparatus is further operative to block signals at the CLK input pin from reaching said at least one latch storage device in the presence of a selected signal at the transparency enable pin.
Claim 7
Dependent Claim
44 words
Transparent bistable storage apparatus according to claim 1 wherein said apparatus is further operative to prevent a signal at said transparency enable pin from reaching said at least one latch storage device in the presence of a selected signal at said SCAN input pin.
Claim 8
Dependent Claim
58 words
Transparent bistable storage apparatus according to claim 1 wherein said apparatus being further operative to pass signals at the D input pin and to pass signals at the CLK input pin to said at least one latch storage device such that the signals at the D input pin are latched through said at least one latch storage device.
Claim 9
Dependent Claim
58 words
Transparent bistable storage apparatus according to claim 5 wherein said apparatus being further operative to pass signals at the D input pin and to pass signals at the CLK input pin to said at least one latch storage device such that the signals at the D input pin are latched through said at least one latch storage device.
Claim 10
Dependent Claim
52 words
Transparent bistable storage apparatus according to claim 2 wherein said apparatus being further operative such that when a selected signal appears at said transparency enable pin, data appearing at said D input pin will pass directly through said at least one latch storage device to said at least one Q output port.
Claim 11
Dependent Claim
43 words
Transparent bistable storage apparatus according to claim 2 wherein said apparatus is further operative to block signals at the CLK input pin from reaching said at least one latch storage device in the presence of a selected signal at the transparent enable pin.
Claim 12
Dependent Claim
44 words
Transparent bistable storage apparatus according to claim 2 wherein said apparatus is further operative to prevent a signal at said transparent enable pin from reaching said at least one latch storage device in the presence of a selected signal at said SCAN input pin.
Claim 13
Dependent Claim
58 words
Transparent bistable storage apparatus according to claim 2 wherein said apparatus being further operative to pass signals at the D input pin and to pass signals at the CLK input pin to said at least one latch storage device such that the signals at the D input pin are latched through said at least one latch storage device.
Claim 14
Dependent Claim
58 words
Transparent bistable storage apparatus according to claim 10 wherein said apparatus being further operative to pass signals at the D input pin and to pass signals at the CLK input pin to said at least one latch storage device such that the signals at the D input pin are latched through said at least one latch storage device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-15 | 1998-11-14 | 1999-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-15 | 2002-11-14 | 2003-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-15 | 2006-11-14 | 2007-05-16 | $7700.00 | Window Closed / Lapsed |