US5155382A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-stage CMOS latch with single-wire clock
Assignee: Hewlett Packard Development Co LP
•
Filing: 1992-02-07
•
Granted: 1992-10-13
•
Expires: 2012-02-07
Abstract
Abstract A master/slave latch circuit employs a single-wire clock, with the clock being applied to only N-channel transistors in the master latch and to only P-channel transistors in the slave latch so that a race-through condition is alleviated in the event of clock skew. The circuits are of ratioless operation, since P-channel transistors are used in each circuit to pull the high side to the supply voltage, and N-channel transistors are used on the low side to assure a zero voltage level. Input to each latch is to the gates of a P-channel pull-up and an N-channel pull-down, while the storage node is between the two clocked transistors. The level of the storage node is inverted and fed back to at transistor across one of the clocked transistors, the one on the high side for the master latch and the low side for the slave latch, and these feedback transistors are of a channel type to support the ratioless scheme.
Inventors
- 👤 William C. Madden
- 👤 Vidya Rajagopalan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3562; H03K3/35625
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
304 words
A CMOS logic circuit comprising: a) a first latch circuit having a first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; a juncture between said second and third transistors being connected through an inverter to an output for said first latch circuit; said output for said first latch circuit being connected to a gate of a fifth transistor having a source-to-drain path connected across said second transistor; said first and fourth transistors being of opposite channel conductivity type; said gates of said first and fourth transistors being connected to a logic input; b) a second latch circuit having first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; a juncture between said second and third transistors being connected through an inverter to an output for said second latch circuit; said output for said second latch circuit being connected to a gate of a fifth transistor having a source-to-drain path connected across said third transistor; said first and fourth transistors of the second latch circuit being of opposite channel conductivity type; said gates of said first and fourth transistors of said second latch circuit being connected to said output of said first latch circuit; c) a single clock voltage connected to said gates of said second and third transistors of said first latch circuit and to said gates of said second and third transistors of said second latch circuit; said second and third transistors of said first latch circuit being of opposite channel conductivity type than said second and third transistors of said second latch circuit.
Claim 2
Dependent Claim
304 words
A CMOS logic circuit comprising: a) a first latch circuit having a first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; a juncture between said second and third transistors being connected through an inverter to an output for said first latch circuit; said output for said first latch circuit being connected to a gate of a fifth transistor having a source-to-drain path connected across said second transistor; said first and fourth transistors being of opposite channel conductivity type; said gates of said first and fourth transistors being connected to a logic input; b) a second latch circuit having first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; a juncture between said second and third transistors being connected through an inverter to an output for said second latch circuit; said output for said second latch circuit being connected to a gate of a fifth transistor having a source-to-drain path connected across said third transistor; said first and fourth transistors of the second latch circuit being of opposite channel conductivity type; said gates of said first and fourth transistors of said second latch circuit being connected to said output of said first latch circuit; c) a single clock voltage connected to said gates of said second and third transistors of said first latch circuit and to said gates of said second and third transistors of said second latch circuit; said second and third transistors of said first latch circuit being of opposite channel conductivity type than said second and third transistors of said second latch circuit.
Claim 3
Dependent Claim
32 words
A circuit according to claim 1 wherein said second and third transistors of said first latch circuit are N-channel, and said second and third transistors of said second latch circuit are P-channel.
Claim 4
Dependent Claim
28 words
A circuit according to claim 2 wherein said fifth transistor of said first latch circuit is P-channel, and said fifth transistor of said second latch circuit is N-channel.
Claim 5
Dependent Claim
34 words
A circuit according to claim 3 wherein said first transistors of both said first and second latch circuits are P-channel, and said fourth transistors of both said first and second latch circuits are N-channel.
Claim 6
Dependent Claim
51 words
A circuit according to claim 1 wherein said clock voltage has a first state and a second state, said first latch circuit passing data during said first state and latching during said second state, and said second latch circuit passing data during said second state and latching during said first state.
Claim 7
Dependent Claim
22 words
A circuit according to claim 5 wherein said first state is a positive voltage and said second state is a zero voltage.
Claim 8
Dependent Claim
344 words
A CMOS master/slave latch circuit comprising: a) a master latch circuit having a first input P-channel transistor in series with a first clocked N-channel transistor, said first input P-channel transistor and said first clocked N-channel transistor having source-to-drain paths in series between a terminal of a voltage supply and an intermediate node; and having a second input N-channel transistor in series with a second clocked N-channel transistor, said second input N-channel transistor and said second clocked N-channel transistor having source-to-drain paths in series between another terminal of said voltage supply and said intermediate node; said intermediate node being connected through an inverter to an output for said master latch circuit; said output for said master latch circuit being connected to a gate of a third P-channel transistor having a source-to-drain path connected across said first clocked N-channel transistor; said first input P-channel transistor and said second input N-channel transistor having gates connected to a circuit input; b) a slave latch circuit having a first input P-channel transistor in series with a first clocked P-channel transistor, said input P-channel transistor and said first clocked P-channel transistor having source-to-drain paths in series between a terminal of a voltage supply and an intermediate node; and having a second input N-channel transistor in series with a second clocked P-channel transistor, said second input N-channel transistor and said second clocked P-channel transistor, having source-to-drain paths in series between another terminal of said voltage supply and said intermediate node; said intermediate node being connected through an inverter to an output for said slave latch circuit; said output for said slave latch circuit being connected to a gate of a third N-channel transistor having a source-to-drain path connected across said second clocked P-channel transistor; said first input P-channel transistor and said second input N-channel transistor having gates coupled to said output for said master latch circuit; c) a single clock voltage connected to gates of said first and second clocked transistors of said master latch circuit and to gates of said first and second clocked transistors of said slave latch circuit.
Claim 9
Dependent Claim
344 words
A CMOS master/slave latch circuit comprising: a) a master latch circuit having a first input P-channel transistor in series with a first clocked N-channel transistor, said first input P-channel transistor and said first clocked N-channel transistor having source-to-drain paths in series between a terminal of a voltage supply and an intermediate node; and having a second input N-channel transistor in series with a second clocked N-channel transistor, said second input N-channel transistor and said second clocked N-channel transistor having source-to-drain paths in series between another terminal of said voltage supply and said intermediate node; said intermediate node being connected through an inverter to an output for said master latch circuit; said output for said master latch circuit being connected to a gate of a third P-channel transistor having a source-to-drain path connected across said first clocked N-channel transistor; said first input P-channel transistor and said second input N-channel transistor having gates connected to a circuit input; b) a slave latch circuit having a first input P-channel transistor in series with a first clocked P-channel transistor, said input P-channel transistor and said first clocked P-channel transistor having source-to-drain paths in series between a terminal of a voltage supply and an intermediate node; and having a second input N-channel transistor in series with a second clocked P-channel transistor, said second input N-channel transistor and said second clocked P-channel transistor, having source-to-drain paths in series between another terminal of said voltage supply and said intermediate node; said intermediate node being connected through an inverter to an output for said slave latch circuit; said output for said slave latch circuit being connected to a gate of a third N-channel transistor having a source-to-drain path connected across said second clocked P-channel transistor; said first input P-channel transistor and said second input N-channel transistor having gates coupled to said output for said master latch circuit; c) a single clock voltage connected to gates of said first and second clocked transistors of said master latch circuit and to gates of said first and second clocked transistors of said slave latch circuit.
Claim 10
Dependent Claim
52 words
A circuit according to claim 7 wherein said single clock voltage has a first state and a second state, said master latch circuit passing data during said first state and latching during said second state, and said slave latch circuit passing data during said second state and latching during said first state.
Claim 11
Dependent Claim
22 words
A circuit according to claim 7 wherein said first state is a positive voltage and said second state is a zero voltage.
Claim 12
Dependent Claim
17 words
A circuit according to claim 7 wherein said voltage supply has a positive and a ground terminal.
Claim 13
Independent Claim
337 words
A method of operating a CMOS master/slave latch circuit, comprising the steps of: a) applying a data input to gates of first and fourth transistors of a master latch circuit having a first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; said first and fourth transistors being of opposite channel conductivity type; b) connecting a juncture between said second and third transistors of said master latch circuit through an inverter to an output for said master latch circuit; c) connecting said output for said master latch circuit to a gate of a fifth transistor having a source-to-drain path connected across said second transistor;; said gates of said first and fourth transistors being connected to a logic input; d) applying said output for said master latch circuit to gates of first and fourth transistors of a slave latch circuit first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; said first and fourth transistors of the slave latch circuit being of opposite channel conductivity type; e) connecting a juncture between said second and third transistors of said slave latch circuit through an inverter to an output for said slave latch circuit; f) connecting said output for said slave latch circuit to a gate of a fifth transistor of said slave latch circuit having a source-to-drain path connected across said third transistor of said slave latch circuit; and g) applying a single clock voltage to said gates of said second and third transistors of said master latch circuit and to said gates of said second and third transistors of said slave latch circuit; said second and third transistors of said master latch circuit being of opposite channel conductivity type than said second and third transistors of said slave latch circuit.
Claim 14
Independent Claim
337 words
A method of operating a CMOS master/slave latch circuit, comprising the steps of: a) applying a data input to gates of first and fourth transistors of a master latch circuit having a first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; said first and fourth transistors being of opposite channel conductivity type; b) connecting a juncture between said second and third transistors of said master latch circuit through an inverter to an output for said master latch circuit; c) connecting said output for said master latch circuit to a gate of a fifth transistor having a source-to-drain path connected across said second transistor;; said gates of said first and fourth transistors being connected to a logic input; d) applying said output for said master latch circuit to gates of first and fourth transistors of a slave latch circuit first, second, third and fourth transistors, each having a source-to-drain path and a gate, said source-to-drain paths of said transistors being connected in series in the order named between terminals of a voltage supply; said first and fourth transistors of the slave latch circuit being of opposite channel conductivity type; e) connecting a juncture between said second and third transistors of said slave latch circuit through an inverter to an output for said slave latch circuit; f) connecting said output for said slave latch circuit to a gate of a fifth transistor of said slave latch circuit having a source-to-drain path connected across said third transistor of said slave latch circuit; and g) applying a single clock voltage to said gates of said second and third transistors of said master latch circuit and to said gates of said second and third transistors of said slave latch circuit; said second and third transistors of said master latch circuit being of opposite channel conductivity type than said second and third transistors of said slave latch circuit.
Claim 15
Dependent Claim
52 words
A method according to claim 11 wherein said single clock voltage has a first state and a second state, said master latch circuit passing data during said first state and latching during said second state, and said slave latch circuit passing data during said second state and latching during said first state.
Claim 16
Dependent Claim
22 words
A method according to claim 12 wherein said first state is a positive voltage and said second state is a zero voltage.
Claim 17
Dependent Claim
17 words
A method according to claim 13 wherein said voltage supply has a positive and a ground terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |