US5414827A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic cache flush
Assignee: OPTI Inc A CORP OF
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Filing: 1991-12-19
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Granted: 1995-05-09
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Expires: 2011-12-19
Abstract
Abstract According to the invention, a chipset is provided which powers up in a default state with caching disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while caching is disabled. Even though no "valid" bit is cleared, erroneous cache hits after caching is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway.
Inventors
- 👤 Fong-Lu Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:33
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F12/0804; G06F12/0891; G06F12/0215
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
450 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps, in response to a read access to a provided secondary memory read address, of: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications, said method further comprising the step of invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said step of invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 2
Independent Claim
450 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps, in response to a read access to a provided secondary memory read address, of: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications, said method further comprising the step of invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said step of invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 3
Dependent Claim
37 words
A method according to claim 1, wherein said tag written into the tag portion of said selected entry in said step of invalidating said selected cache memory entry, is derived from said provided secondary memory read address.
Claim 4
Dependent Claim
23 words
A method according to claim 1, wherein said first secondary memory address range which is defined as noncacheable is defined as permanently noncacheable.
Claim 5
Independent Claim
449 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps, in response to each read access to a provided secondary memory read address, of: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications, said method further comprising the step of invalidating said given cache memory entry if caching is disabled, by, if caching is disabled, writing into the tag portion of said given entry a tag which associates said entry with a secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said step of invalidating said given cache memory entry eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 6
Independent Claim
449 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps, in response to each read access to a provided secondary memory read address, of: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications, said method further comprising the step of invalidating said given cache memory entry if caching is disabled, by, if caching is disabled, writing into the tag portion of said given entry a tag which associates said entry with a secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said step of invalidating said given cache memory entry eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 7
Dependent Claim
15 words
A method according to claim 4, wherein said computer system powers up with caching disabled.
Claim 8
Independent Claim
456 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps of: flushing said cache memory by writing into the tag portion of each particular one of said cache memory entries a respective tag which associates said particular entry with a respective secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said method further comprising the steps of, in response to a read access to a provided secondary memory read address, which read access occurs subsequently to said step of flushing: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications; said step of flushing said cache memory entry eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 9
Independent Claim
456 words
A method for managing a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said method comprising the steps of: flushing said cache memory by writing into the tag portion of each particular one of said cache memory entries a respective tag which associates said particular entry with a respective secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said method further comprising the steps of, in response to a read access to a provided secondary memory read address, which read access occurs subsequently to said step of flushing: returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; and generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable; and returning data from said secondary memory instead of said cache memory in response to said cache miss indications; said step of flushing said cache memory entry eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 10
Dependent Claim
312 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, said control apparatus comprising: means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and means for invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a first tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said means for invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit from each entry of said cache memory.
Claim 11
Dependent Claim
312 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, said control apparatus comprising: means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and means for invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a first tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said means for invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit from each entry of said cache memory.
Claim 12
Dependent Claim
42 words
Apparatus according to claim 7, for use further with a cache enablement signal indicating whether caching is enabled, wherein said means for returning data from the data portion of one of said cache memory entries, returns data only if caching is enabled.
Claim 13
Dependent Claim
26 words
Apparatus according to claim 7, wherein said mapping maps each of said secondary memory data lines to no more than one of said cache memory entries.
Claim 14
Dependent Claim
20 words
Apparatus according to claim 7, wherein said first secondary memory address range which is defined as noncacheable, is permanently noncacheable.
Claim 15
Dependent Claim
20 words
Apparatus according to claim 7, further comprising a writable memory defining whether said first secondary memory address range is noncacheable.
Claim 16
Dependent Claim
20 words
Apparatus according to claim 7, further comprising means for deriving said first tag from said provided secondary memory read address.
Claim 17
Dependent Claim
463 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said control apparatus comprising: means for, in response to each read access to a provided secondary memory read address, returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; means for, in response to each of said read accesses, generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; means for, in response to each of said read accesses, generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable, means for returning data from said secondary memory instead of said cache memory in response to said cache miss indications; and invalidating means for, in response to each of said read accesses which occurs while caching is disabled, writing into the tag portion of said given entry a tag which associates said entry with a secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said invalidating means eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 18
Dependent Claim
463 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, for use further in a computer system permitting enablement and disablement of caching, said control apparatus comprising: means for, in response to each read access to a provided secondary memory read address, returning data from the data portion of a given one of said cache memory entries, which entry maps to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, only if (a) the tag portion of said given cache memory entry associates said given entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address, (b) said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable, and (c) caching is enabled; means for, in response to each of said read accesses, generating a cache miss indication if the tag portion of none of the cache memory entries which map to the secondary memory data line containing the data bytes designated by the provided secondary memory read address, associates its entry with the secondary memory data line containing the data bytes designated by the provided secondary memory read address; means for, in response to each of said read accesses, generating a cache miss indication also if said provided secondary memory read address is within one of said secondary memory address ranges which is defined as noncacheable, means for returning data from said secondary memory instead of said cache memory in response to said cache miss indications; and invalidating means for, in response to each of said read accesses which occurs while caching is disabled, writing into the tag portion of said given entry a tag which associates said entry with a secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said invalidating means eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 19
Dependent Claim
14 words
Apparatus according to claim 13, wherein said computer system powers up with caching disabled.
Claim 20
Dependent Claim
300 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, said control apparatus comprising: means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and cache flushing means for writing into the tag portion of each particular one of said cache memory entries a respective tag which associates said particular entry with a respective secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said cache flushing means eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 21
Dependent Claim
300 words
Cache memory control apparatus, for use with a cache memory having a plurality of entries, each entry having a tag portion and a data portion, for use further with a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines, said cache memory having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable, said control apparatus comprising: means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and cache flushing means for writing into the tag portion of each particular one of said cache memory entries a respective tag which associates said particular entry with a respective secondary memory data line that is within one of said secondary memory address ranges which is defined as noncacheable, said cache flushing means eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 22
Dependent Claim
300 words
Computer apparatus comprising: a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines; a cache memory having a plurality of entries, each entry having a tag portion and a data portion, said computer apparatus having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable; means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and means for invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a first tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said means for invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit for each entry of said cache memory.
Claim 23
Dependent Claim
300 words
Computer apparatus comprising: a secondary memory having storage for bytes of data at secondary memory addresses, said storage being organized into a plurality of secondary memory data lines, each of said secondary memory addresses designating at least one of the data bytes in one of said secondary memory data lines; a cache memory having a plurality of entries, each entry having a tag portion and a data portion, said computer apparatus having a mapping which maps each cache memory entry to a predetermined plurality of said secondary memory data lines, each cache memory entry being associated, according to a tag in its tag portion, with at most one of the secondary memory data lines to which the entry maps, at least one range of secondary memory addresses being defined as noncacheable; means for returning data from said secondary memory in response to a memory read request to a provided secondary memory read address, if said provided secondary memory read address is within one of said secondary memory address ranges which are defined as noncacheable; means for returning data from the data portion of one of said cache memory entries in response to said provided secondary memory read address, only if said provided secondary memory read address is outside of all of said secondary memory address ranges which are defined as noncacheable; and means for invalidating a selected one of said cache memory entries by writing into the tag portion of said selected entry a first tag which associates said selected entry with a secondary memory data line that is within a first one of said secondary memory address ranges which is defined as noncacheable, said means for invalidating a selected one of said cache memory entries eliminating a requirement for a tag-valid bit for each entry of said cache memory.
References Cited (Backward Citations)
US4426682A
Cited
US4493026A
Cited
US4713755A
Cited
US4794523A
Cited
US4953073A
Cited
US5113506A
Cited
US5091846A
Cited
US4831581A
Cited
US5091845A
Cited
US4831520A
Cited
US4920477A
Cited
US4833599A
Cited
US5057837A
Cited
US4959777A
Cited
US5091850A
Cited
US5157774A
Cited
US4847758A
Cited
US5008813A
Cited
US5045998A
Cited
US5095428A
Cited
US5097532A
Cited
US5119485A
Cited
US5247648A
Cited
US5210850A
Cited
US5276833A
Cited
US5293603A
Cited
USPTO Annuity & Maintenance Windows
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| 7.5 Years (Year 8) | 2002-05-08 | 2002-11-07 | 2003-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-08 | 2006-11-07 | 2007-05-09 | $7700.00 | Window Closed / Lapsed |