Electrically erasable programmable read-only memory array

Claim 2

A memory array operative at different times in an erase mode, a program mode, and a read mode, comprising: a first settable threshold memory cell having a control terminal and first and second controlled terminals, wherein the threshold is set by application of a voltage across the control terminal and the first controlled terminal thereof; a second settable threshold memory cell having a control terminal and first and second controlled terminals, wherein the threshold is set by application of a voltage across the control terminal and the first controlled terminal thereof; a first switch having a control terminal and first and second controlled terminals; a second switch having a control terminal and first and second controlled terminals; an array reference line connected to the respective first controlled terminals of the first and second switches, the respective second controlled terminals of the first and second switches being connected to one another by a common line; a bit line connected to the respective first controlled terminals of the first and second memory cells, the respective second controlled terminals of the first and second switches being connected to the common line; a first word line connected to the respective control terminals of the first memory cell and the first switch; and a second word line connected to the respective control terminals of the second memory cell and the second switch.

Claim 3

A memory array as in claim 1, wherein: the first and second word lines are operative in the erase mode to apply, in conjunction with the bit line, a high level voltage of a first polarity across a particular one or more of the first and second memory cells; the first and second word lines are operative in the program mode to apply, in conjunction with the bit line, a high level voltage of a second polarity opposite the first polarity to a particular one or more of the first and second memory cells; the first word line is operative in the read mode to select at particular times the first memory cell by application of a low level voltage to the control terminal thereof; and the second word line is operative in the read mode to select at particular times the second memory cell by application of a low level voltage to the control terminal thereof.

Claim 4

A memory array comprising: a first adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a second adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a first switch transistor having a gate and first and second current terminals; a second switch transistor having a gate and first and second current terminals; an array reference line connected to the first current terminals of the first and second switches; a common line connected to the second current terminals of the first and second switches and the second current terminals of the first and second adjustable threshold transistors; a bit line connected to the first current terminals of the first and second adjustable threshold transistors; a first word line connected to the gates of the first adjustable threshold transistor and the first switch; and a second word line connected to the gates of the second adjustable threshold transistor and the second switch.

Claim 5

A memory array comprising: a first adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a second adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a first switch transistor having a gate and first and second current terminals; a second switch transistor having a gate and first and second current terminals; an array reference line connected to the first current terminals of the first and second switches; a common line connected to the second current terminals of the first and second switches and the second current terminals of the first and second adjustable threshold transistors; a bit line connected to the first current terminals of the first and second adjustable threshold transistors; a first word line connected to the gates of the first adjustable threshold transistor and the first switch; and a second word line connected to the gates of the second adjustable threshold transistor and the second switch.

Claim 6

A memory array as in claim 3 further comprising a sense circuit controllably connected to the bit line, the first and second adjustable threshold transistors generally conducting a first current value when in depletion and generally conducting a second current when on, and the sense circuit having a current sensing threshold between the first and second current values.

Claim 7

A memory array as in claim 4 further comprising: a column select terminal; and a third switch transistor having a gate connected to the column select terminal, the sense circuit being a sense amplifier controllably connected to the bit line through the third switch transistor.

Claim 8

A memory array as in claim 5 further comprising: a precharge control terminal; a voltage node; and a fourth switch transistor having a gate connected to the precharge control terminal, the voltage node being controllably connected to the bit line through the fourth switch transistor.

Claim 9

A memory array as in claim 3 further comprising a latch controllably connected to the bit line.

Claim 10

A memory array as in claim 7 further comprising: a load terminal; and a third switch transistor having a gate connected to the load terminal, the latch being a pair of cross-coupled inverters controllably connected to the bit line through the third switch transistor.

Claim 11

A memory array as in claim 3 operative at different times in an erase mode, a program mode, and a read mode, further comprising: means for applying in erase mode a first erase voltage on the bit line and a second erase voltage on the first word line, the first erase voltage being of a value relative to the second erase voltage to establish a low threshold voltage on the first adjustable threshold transistor by Fowler-Nordheim tunneling from the first current terminal of the first adjustable threshold transistor to the floating gate of the first adjustable threshold transistor; and means for applying in program mode a first program voltage on the bit line and a second program voltage on the first word line, the first program voltage being of a value relative to the second program voltage to establish a high threshold voltage on the first adjustable threshold transistor by Fowler-Nordheim tunneling from the floating gate of the first adjustable threshold transistor to the first current terminal of the first adjustable threshold transistor.

Claim 12

A method for operating a memory array as in claim 3 in, at different times, and erase mode and a write mode, comprising the steps of: furnishing a first erase mode voltage on the bit line; furnishing a second erase mode voltage on the first word line, the second erase mode voltage being of a first polarity and having a magnitude relative to the first erase mode voltage so that a first threshold voltage indicative of a first logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor; furnishing a first program mode voltage on the bit line indicative of a second logical state opposite the first logical state; and furnishing a second program mode voltage on the first word line, the second program mode voltage being of a second polarity opposite the first polarity and having a magnitude relative to the first program mode voltage so that a second threshold voltage indicative of the second logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor.

Claim 13

A method as in claim 10 wherein the first erase mode voltage is zero volts indicative of a logical one, the second erase mode voltage is twenty volts, the first program mode voltage is five volts indicative of a logical zero, and the second program mode voltage is minus fifteen volts.

Claim 14

A method as in claim 10 further comprising the step of furnishing the first erase mode voltage as a substrate bias for the first adjustable threshold transistor so that establishment of the first threshold voltage indicative of a first logical state in the first adjustable threshold transistor is assisted by Fowler-Nordheim tunneling between the substrate and the floating gate of the first adjustable threshold transistor.

Claim 15

A method as in claim 12 wherein the first erase mode voltage is minus four volts indicative of a logical one, the second erase mode voltage is fifteen volts, the first program mode voltage is five volts indicative of a logical zero, and the second program mode voltage is minus fifteen volts.

Claim 16

A method as in claim 10 further comprising the steps of: furnishing a third erase mode voltage on the second word line, the third erase mode voltage being of a polarity and magnitude relative to the first erase mode voltage to avoid Fowler-Nordheim tunneling between the first current terminal and the floating gate of the second adjustable threshold transistor, wherein a threshold voltage state of the second adjustable threshold transistor is unchanged; and furnishing a third program mode voltage on the second word line, the third program voltage being of a polarity and magnitude relative to the first program mode voltage to avoid Fowler-Nordheim tunneling between the first current terminal and the floating gate of the second adjustable threshold transistor, wherein a threshold voltage state of the second adjustable threshold transistor is unchanged.

Claim 17

A method as in claim 14 wherein the polarity and magnitude of the third program mode voltage is equal to or less than an anticipated negative threshold voltage of the second adjustable threshold transistor to ensure that no conduction path forms therethrough.

Claim 18

A method as in claim 15 wherein the first erase mode voltage is zero volts indicative of a logical one, the second erase mode voltage is twenty volts, the third erase mode voltage is zero volts, the first program mode voltage is five volts indicative of a logical zero, the second program mode voltage is minus fifteen volts, and the third program mode voltage is minus one volt.

Claim 19

A method as in claim 10 further comprising the steps of: furnishing the second erase mode voltage on the second word line so that a first threshold voltage indicative of a first logical state is established in the second adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the second adjustable threshold transistor; and furnishing a third program mode voltage on the second word line, the third program voltage being of a polarity and magnitude relative to the first program mode voltage to avoid Fowler-Nordheim tunneling between the first current terminal and the floating gate of the second adjustable threshold transistor so that a threshold voltage state of the second adjustable threshold transistor is unchanged.

Claim 20

A method as in claim 17 wherein the polarity and magnitude of the third program mode voltage is equal to or less than an anticipated negative threshold voltage of the second adjustable threshold transistor to ensure that no conduction path forms therethrough.

Claim 21

A method as in claim 18 wherein the first erase mode voltage is zero volts indicative of a logical one, the second erase mode voltage is twenty volts, the first program mode voltage is five volts indicative of a logical zero, the second program mode voltage is minus fifteen volts, and the third program mode voltage is minus one volt.

Claim 22

A method for operating a memory array as in claim 3 in, at different times, and erase mode and a write mode, comprising the steps of: furnishing a first erase mode voltage on the bit line; furnishing a second erase mode voltage on the first word line, the second erase voltage being of a first polarity and having a magnitude relative to the first erase mode voltage so that a first threshold voltage indicative of a first logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor; furnishing on the bit line at different times a first program mode voltage indicative of a second logical state opposite the first logical state, and a second program mode voltage indicative of the first logic state; and furnishing a third program mode voltage on the first word line, the third program mode voltage being of a second polarity opposite the first polarity, having a magnitude relative to the first program voltage so that a second threshold voltage indicative of the second logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor, and having a magnitude relative to the second program mode voltage to avoid Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor so that a threshold voltage state of the first adjustable threshold transistor is unchanged.

Claim 23

A method as in claim 20 wherein the first erase mode voltage is zero volts indicative of a logical one, the second erase mode voltage is twenty volts, the first program mode voltage is five volts indicative of a logical zero, the second program mode voltage is zero volts indicative of a logical one, and the third program mode voltage is minus fifteen volts.

Claim 24

A method as in claim 20 wherein the first erase mode voltage is zero volts indicative of a logical one, the second erase mode voltage is twenty volts, the first program mode voltage is five volts indicative of a logical zero, the second program mode voltage is a floating condition indicative of a logical one, and the third program mode voltage is minus fifteen volts.

Claim 25

A method for operating a memory array as in claim 3 in a read mode, wherein the first adjustable threshold transistor is set at a threshold value indicative of a logical state, the threshold value being one of a low threshold indicative of a first logical state and a high threshold indicative of a second logical state, comprising the steps of: furnishing a first read mode voltage on the bit line; and furnishing a second read mode voltage on the first word line, the second read mode voltage being of a value to cause the first adjustable threshold transistor to conduct when the threshold value thereof is a low threshold, and to avoid causing conduction in the first adjustable threshold transistor when the threshold value thereof is a high threshold.

Claim 26

A method as in claim 23 wherein the first read mode voltage is 1.5 volts, and the second read mode voltage is 2.5 volts.

Claim 27

A method as in claim 23 wherein the first and second adjustable threshold transistors generally conduct a first current value when in depletion and generally conduct a second current when the second read mode voltage is applied thereto, and wherein the first read mode voltage is a precharge voltage, further comprising the step of sensing current flow on the bit line with a sensing threshold between the first and second current values.

Claim 28

A memory array comprising: a first subarray comprising: a first adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a second adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; and a first common node, the second current terminals of the first and second adjustable threshold transistors being connected to the first common node; a second subarray comprising: a third adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a fourth adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; and a second common node, the second current terminals of the first and second adjustable threshold transistors being connected to the second common node; a first word line connected to the gate of the first adjustable threshold transistor; a second word line connected to the gate of the second adjustable threshold transistor; a third word line connected to the gate of the third adjustable threshold transistor; a fourth word line connected to the gate of the fourth adjustable threshold transistor; and a bit line connected to the first current terminals of the first, second, third and fourth adjustable threshold transistors; wherein the first common node is at a reference potential when either of the first and second word lines is selected, and is at a potential determined by the bit line when neither of the first and second word lines is selected and either of the first and second adjustable threshold transistors is in depletion; and wherein the second common node is at a reference potential when either of the third and fourth word lines is selected, and is at a potential determined by the bit line when neither of the third and fourth word lines is selected and either of the third and fourth adjustable threshold transistors is in depletion.

Claim 29

A memory array comprising: a first subarray comprising: a first adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a second adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; and a first common node, the second current terminals of the first and second adjustable threshold transistors being connected to the first common node; a second subarray comprising: a third adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the first adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; a fourth adjustable threshold transistor having a gate, a floating gate, and first and second current terminals, the second adjustable threshold transistor supporting Fowler-Nordheim tunneling between the first current terminal and the floating gate thereof; and a second common node, the second current terminals of the first and second adjustable threshold transistors being connected to the second common node; a first word line connected to the gate of the first adjustable threshold transistor; a second word line connected to the gate of the second adjustable threshold transistor; a third word line connected to the gate of the third adjustable threshold transistor; a fourth word line connected to the gate of the fourth adjustable threshold transistor; and a bit line connected to the first current terminals of the first, second, third and fourth adjustable threshold transistors; wherein the first common node is at a reference potential when either of the first and second word lines is selected, and is at a potential determined by the bit line when neither of the first and second word lines is selected and either of the first and second adjustable threshold transistors is in depletion; and wherein the second common node is at a reference potential when either of the third and fourth word lines is selected, and is at a potential determined by the bit line when neither of the third and fourth word lines is selected and either of the third and fourth adjustable threshold transistors is in depletion.

Claim 30

A memory array as in claim 26 further comprising a sense circuit controllably connected to the bit line, the first, second, third and fourth adjustable threshold transistors generally conducting a first current value when in depletion and generally conducting a second current when on, and the sense circuit having a current sensing threshold between the first and second current values.

Claim 31

A memory array as in claim 27 further comprising: a precharge control terminal; a voltage node; and a switch connected to the precharge control terminal, the voltage node being controllably connected to the bit line through the switch for precharging the bit line prior to a read cycle.

Claim 32

A memory array as in claim 26 further comprising an array reference voltage line, wherein: the first subarray further comprises: a first switch transistor having a gate connected to the first word line, a first current terminal connected to the array reference voltage line, and a second current terminal connected to the first common node; and a second switch transistor having a gate connected to the second word line, a first current terminal connected to the array reference voltage line, and a second current terminal connected to the first common node; and the second subarray further comprises: a third switch transistor having a gate connected to the third word line, a first current terminal connected to the array reference voltage line, and a second current terminal connected to the second common node; and a fourth switch transistor having a gate connected to the fourth word line, a first current terminal connected to the array reference voltage line, and a second current terminal connected to the second common node.

Claim 33

A method for operating a memory array as in claim 27 in, at different times, and erase mode and a write mode, comprising the steps of: furnishing a first erase mode voltage on the bit line; furnishing a second erase mode voltage on the first word line, the second erase mode voltage being of a first polarity and having a magnitude relative to the first erase mode voltage so that a first threshold voltage indicative of a first logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor; furnishing a first program mode voltage on the bit line indicative of a second logical state opposite the first logical state; and furnishing a second program mode voltage on the first word line, the second program mode voltage being of a second polarity opposite the first polarity and having a magnitude relative to the first program mode voltage so that a second threshold voltage indicative of the second logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor.

Claim 34

A method for operating a memory array as in claim 27 in, at different times, and erase mode and a write mode, comprising the steps of: furnishing a first erase mode voltage on the bit line; furnishing a second erase mode voltage on the first word line, the second erase voltage being of a first polarity and having a magnitude relative to the first erase mode voltage so that a first threshold voltage indicative of a first logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor; furnishing on the bit line at different times a first program mode voltage indicative of a second logical state opposite the first logical state, and a second program mode voltage indicative of the first logic state; and furnishing a third program mode voltage on the first word line, the third program mode voltage being of a second polarity opposite the first polarity, having a magnitude relative to the first program voltage so that a second threshold voltage indicative of the second logical state is established in the first adjustable threshold transistor by Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor, and having a magnitude relative to the second program mode voltage to avoid Fowler-Nordheim tunneling between the first current terminal and the floating gate of the first adjustable threshold transistor so that a threshold voltage state of the first adjustable threshold transistor is unchanged.

Claim 35

A method for operating a memory array as in claim 27 in a read mode, wherein the first adjustable threshold transistor is set at a threshold value indicative of a logical state, the threshold value being one of a low threshold indicative of a first logical state and a high threshold indicative of a second logical state, comprising the steps of: furnishing a first read mode voltage on the bit line; and furnishing a second read mode voltage on the first word line, the second read mode voltage being of a value to cause the first adjustable threshold transistor to conduct when the threshold value thereof is a low threshold, and to avoid causing conduction in the first adjustable threshold transistor when the threshold value thereof is a high threshold.