Method of making trench EEPROM structure on SOI with dual channels

Claim 1

A fabrication method for a trench memory structure including memory cells having dual channels comprising the steps of: step 1, depositing a layer of silicon dioxide on silicon-on-insulator substrate consisting of a layer of silicon on a layer of insulation, step 2, depositing a layer of nitride on said layer of silicone dioxide deposited in step 1, step 3, removing selected portions and leaving remaining portions of said nitride and silicon dioxide layers on said silicon-on-insulator substrate, step 4, removing selected portions and leaving remaining portions of said silicon layer of said silicon-on-insulator substrate to form trenches having four vertical sides between said remaining portions of said silicon layer in the areas where said selected portions of said nitride and silicon dioxide layers were removed in step 3, said remaining portions of said silicon layer providing source and drain regions on either of two opposite sides of said trenches, step 5, growing oxide on the four vertical sides of said remaining portions of silicon layer to provide gate oxide regions, step 6, forming a doped polysilicon layer over said trenches to provide floating gate regions in said trenches, step 7, depositing a layer of insulating material over said doped polysilicon layer and a layer of polysilicon over said layer of insulating material to provide wordline regions.