Patent US5411899A successfully refreshed from Google Patents.
US5411899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor fabrication of a twin tub using angled implant
Assignee: AT&T Inc
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Filing: 1993-10-13
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Granted: 1995-05-02
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Expires: 2013-10-13
Abstract
Abstract A method for forming a twin tub semiconductor integrated circuit is disclosed. A portion of a semiconductor substrate is masked by oxide, nitride and photoresist. P-type dopant is directed towards the other portion of the substrate. Subsequently, the photoresist is removed and a protective oxide is grown over the p-tub, thereby driving the dopant into the substrate. Next, an n-type ion implantation is performed to create the n-tub. The n-type ions are directed at the substrate at an angle which is away from normal incidence. The angular direction of the n-type dopants permits the use of smaller screen oxides over the n-tub and smaller protective oxides over the already-formed p-tub. When all of the protective oxides have been removed, the inventive technique provides a twin tub substrate having a comparatively smooth upper surface.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chen-Hua D. Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/07
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
A method of semiconductor integrated circuit formation comprising: forming first and second tubs of first and second conductivity type in first and second portions of a substrate by directing a first conductivity-type dopant species normally at a first portion of said substrate; forming a material layer over said first portion of said substrate; directing a second conductivity-type dopant species at an angle away from normal at a second portion of said substrate; said material layer absorbing said second-type dopant and whereby a first conductivity-type tub is formed in said first portion of said substrate and a second conductivity-type tub is formed in said second portion of said substrate; forming at least one transistor in said first tub and one transistor in said second tub.
Claim 2
Independent Claim
124 words
A method of semiconductor integrated circuit formation comprising: forming first and second tubs of first and second conductivity type in first and second portions of a substrate by directing a first conductivity-type dopant species normally at a first portion of said substrate; forming a material layer over said first portion of said substrate; directing a second conductivity-type dopant species at an angle away from normal at a second portion of said substrate; said material layer absorbing said second-type dopant and whereby a first conductivity-type tub is formed in said first portion of said substrate and a second conductivity-type tub is formed in said second portion of said substrate; forming at least one transistor in said first tub and one transistor in said second tub.
Claim 3
Dependent Claim
13 words
The method of claim 1 in which said first conductivity type is p-type.
Claim 4
Dependent Claim
12 words
The method of claim 1 in which said second conductivity-type is n-type.
Claim 5
Dependent Claim
13 words
The method of claim 1 in which said material layer is silicon dioxide.
Claim 6
Dependent Claim
12 words
The method of claim 1 in which said transistors are MOS transistors.
Claim 7
Independent Claim
234 words
A method of semiconductor integrated circuit formation comprising: forming a first silicon dioxide layer having a thickness less than 100 Å upon a silicon substrate; forming a silicon nitride layer upon said silicon dioxide layer; forming a patterned photoresist upon said silicon nitride layer; said patterned photoresist overlying a second portion of said silicon substrate and not overlying a first portion of said silicon substrate; patterning said silicon dioxide layer, thereby exposing said first portion of said substrate; directing a p-type dopant species normally at said substrate, said p-type dopant species embedding itself in said first portion of said substrate and being absorbed by said patterned photoresist or said silicon nitride layer overlying said second portion of said substrate; removing said photoresist; removing said silicon nitride layer; exposing said substrate to an oxidizing environment, thereby forming a second silicon dioxide layer having a thickness of less than 600 Å overlying said first portion of said substrate; directing an n-type dopant species at an angle away from normal at said substrate, said n-type dopant species embedding itself in said second portion of said substrate and being absorbed by said second silicon dioxide layer; removing said first and second silicon dioxide layers, thereby exposing the surface of said silicon substrate, forming at least one n-channel transistor upon said first portion of said substrate and at least one p-channel transistor upon said second portion of said substrate.
Claim 8
Independent Claim
234 words
A method of semiconductor integrated circuit formation comprising: forming a first silicon dioxide layer having a thickness less than 100 Å upon a silicon substrate; forming a silicon nitride layer upon said silicon dioxide layer; forming a patterned photoresist upon said silicon nitride layer; said patterned photoresist overlying a second portion of said silicon substrate and not overlying a first portion of said silicon substrate; patterning said silicon dioxide layer, thereby exposing said first portion of said substrate; directing a p-type dopant species normally at said substrate, said p-type dopant species embedding itself in said first portion of said substrate and being absorbed by said patterned photoresist or said silicon nitride layer overlying said second portion of said substrate; removing said photoresist; removing said silicon nitride layer; exposing said substrate to an oxidizing environment, thereby forming a second silicon dioxide layer having a thickness of less than 600 Å overlying said first portion of said substrate; directing an n-type dopant species at an angle away from normal at said substrate, said n-type dopant species embedding itself in said second portion of said substrate and being absorbed by said second silicon dioxide layer; removing said first and second silicon dioxide layers, thereby exposing the surface of said silicon substrate, forming at least one n-channel transistor upon said first portion of said substrate and at least one p-channel transistor upon said second portion of said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-01 | 1998-10-31 | 1999-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-01 | 2002-10-31 | 2003-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-01 | 2006-10-31 | 2007-05-02 | $7700.00 | Window Closed / Lapsed |