US5300797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coplanar twin-well integrated circuit structure
Assignee: STMicroelectronics lnc USA
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Filing: 1992-03-31
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Granted: 1994-04-05
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Expires: 2012-03-31
Abstract
Abstract A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys.
Inventors
- 👤 Frank R. Bryant
- 👤 Tsiu C. Chan
- 👤 Kuei-Wu Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10W; H10W46/00; H10W46/301; H10W46/501
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
32 words
A structure in an integrated circuit, comprising: an N-type well in a semiconductor substrate; a P-type well in the semiconductor substrate, wherein the upper surface of the N-well and P-well are coplanar.
Claim 2
Dependent Claim
32 words
A structure in an integrated circuit, comprising: an N-type well in a semiconductor substrate; a P-type well in the semiconductor substrate, wherein the upper surface of the N-well and P-well are coplanar.
Claim 3
Dependent Claim
16 words
The structure of claim 1, further comprising sets of alignment keys formed in a semiconductor wafer.
Claim 4
Dependent Claim
28 words
The structure of claim 2, wherein the sets of alignment keys are formed in a portion of the semiconductor wafer that is not part of the integrated circuit.
Claim 5
Dependent Claim
20 words
The structure of claim 1, further comprising a region of field oxide between the N-type well and the P-type well.
Claim 6
Dependent Claim
29 words
The structure of claim 1, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions.
Claim 7
Dependent Claim
45 words
The structure of claim 1, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, said oxide isolation regions being recessed into said first surface to produce an approximately planar structure.
Claim 8
Dependent Claim
42 words
The structure of claim 1, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, and said oxide isolation regions overlying boundaries between wells of dissimilar conductivity type.
Claim 9
Dependent Claim
185 words
An integrated circuit structure, comprising: a substrate comprising monolithic semiconductor material of a first conductivity at a first surface thereof; a plurality of first well regions, each comprising a diffusion of first-conductivity-type dopant into said semiconductor material, to produce a higher dopant concentration than that of other portions of said semiconductor material; a plurality of second well regions, each comprising a second-conductivity-type diffusion within said semiconductor material; a first plurality of field-effect transistors, each comprising source and drain diffusions of second-conductivity-type dopants at said first surface within a respective one of said first well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a second plurality of field-effect transistors, each comprising source and drain diffusions of first-conductivity-type dopants at said first surface within a respective one of said second well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; wherein said first surface over said first well regions is coplanar with first surface over said second regions.
Claim 10
Dependent Claim
185 words
An integrated circuit structure, comprising: a substrate comprising monolithic semiconductor material of a first conductivity at a first surface thereof; a plurality of first well regions, each comprising a diffusion of first-conductivity-type dopant into said semiconductor material, to produce a higher dopant concentration than that of other portions of said semiconductor material; a plurality of second well regions, each comprising a second-conductivity-type diffusion within said semiconductor material; a first plurality of field-effect transistors, each comprising source and drain diffusions of second-conductivity-type dopants at said first surface within a respective one of said first well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a second plurality of field-effect transistors, each comprising source and drain diffusions of first-conductivity-type dopants at said first surface within a respective one of said second well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; wherein said first surface over said first well regions is coplanar with first surface over said second regions.
Claim 11
Dependent Claim
26 words
An integrated circuit structure of claim 8, wherein some portions of said first surface are not part of said first wells nor of said second wells.
Claim 12
Dependent Claim
14 words
An integrated circuit structure of claim 8, wherein said first conductivity type is P-type.
Claim 13
Dependent Claim
31 words
An integrated circuit structure of claim 8, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions.
Claim 14
Dependent Claim
47 words
An integrated circuit structure of claim 8, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, said oxide isolation regions being recessed into said first surface to produce an approximately planar structure.
Claim 15
Dependent Claim
44 words
An integrated circuit structure of claim 8, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, and said oxide isolation regions overlying boundaries between wells of dissimilar conductivity type.
Claim 16
Dependent Claim
29 words
An integrated circuit structure of claim 8, further comprising a plurality of active device regions within each said wells, said active device regions being separated by oxide isolation regions.
Claim 17
Dependent Claim
14 words
An integrated circuit structure of claim 8, wherein said first conductivity type is P-type.
Claim 18
Dependent Claim
205 words
An integrated circuit structure, unseparated in a wafer form, comprising: a substrate comprising monolithic semiconductor material of a first conductivity at a first surface thereof; a plurality of first well regions, each comprising a diffusion of first-conductivity-type dopant into said semiconductor material, to produce a higher dopant concentration than that of other portions of said semiconductor material; a plurality of second well regions, each comprising a second-conductivity-type diffusion within said semiconductor material; a first plurality of field-effect transistors, each comprising source and drain diffusions of second-conductivity-type dopants at said first surface within a respective one of said first well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a second plurality of field-effect transistors, each comprising source and drain diffusions of first-conductivity-type dopants at said first surface within a respective one of said second well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a plurality of alignment keys, each comprising a recess etched into said first surface; wherein said first surface over said first well regions is coplanar with said first surface over said second regions.
Claim 19
Dependent Claim
205 words
An integrated circuit structure, unseparated in a wafer form, comprising: a substrate comprising monolithic semiconductor material of a first conductivity at a first surface thereof; a plurality of first well regions, each comprising a diffusion of first-conductivity-type dopant into said semiconductor material, to produce a higher dopant concentration than that of other portions of said semiconductor material; a plurality of second well regions, each comprising a second-conductivity-type diffusion within said semiconductor material; a first plurality of field-effect transistors, each comprising source and drain diffusions of second-conductivity-type dopants at said first surface within a respective one of said first well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a second plurality of field-effect transistors, each comprising source and drain diffusions of first-conductivity-type dopants at said first surface within a respective one of said second well regions, and a respective gate capacitively coupled to said first surface to define a controllably conductive path between said source and drain regions; a plurality of alignment keys, each comprising a recess etched into said first surface; wherein said first surface over said first well regions is coplanar with said first surface over said second regions.
Claim 20
Dependent Claim
20 words
An integrated circuit structure of claim 16, wherein said alignment keys are outside of both said first and second wells.
Claim 21
Dependent Claim
20 words
An integrated circuit structure of claim 16, wherein said alignment keys are outside of both said first and second wells.
Claim 22
Dependent Claim
26 words
The integrated circuit structure of claim 16, wherein some portions of said first surface are not part of said first wells nor of said second wells.
Claim 23
Dependent Claim
14 words
The integrated circuit structure of claim 16, wherein said first conductivity type is P-type.
Claim 24
Dependent Claim
31 words
The integrated circuit structure of claim 16, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions.
Claim 25
Dependent Claim
47 words
The integrated circuit structure of claim 16, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, said oxide isolation regions being recessed into said first surface to produce an approximately planar structure.
Claim 26
Dependent Claim
43 words
The integrated circuit structure of claim 16, further comprising a plurality of active device regions within respective ones of said wells, said active device regions being separated by oxide isolation regions, said oxide isolation regions overlying boundaries between wells of dissimilar conductivity type.
Claim 27
Dependent Claim
29 words
The integrated circuit structure of claim 16, further comprising a plurality of active device regions within each said wells, said active device regions being separated by oxide isolation regions.
Claim 28
Dependent Claim
14 words
The integrated circuit structure of claim 16, wherein said first conductivity type is P-type.
References Cited (Backward Citations)
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