Potential data selection circuit

Claim 2

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said multiplexer includes an initial potential setting unit, analog switches each comprised of an N-channel MOS transistor, and a discharging unit, wherein said initial potential setting unit is adapted to set in advance a potential on an output terminal of said multiplexer to an initial potential higher than potentials of said at least two potential data, wherein said analog switches are adapted so that said potential data are respectively given thereto to select any one of said potential data thereby on a basis of said control signals outputted from said decoder to output the selected one thereby, and wherein said discharging unit is adapted to carry out a discharge operation to allow the potential on said output terminal set to said initial potential to fall to a potential of said potential data selected by said analog switches and outputted therefrom, and thus carry out output of said potential data.

Claim 3

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said multiplexer includes an initial potential setting unit, analog switches each comprised of a P-channel MOS transistor, and a potential setting unit is adapted to set in advance a potential on an output terminal of said multiplexer to an initial potential lower than potentials of said at least two potential data, wherein said analog switches are adapted so that said potential data are respectively given thereto to select any one of said potential data thereby on a basis of said control signal outputted from said decoder to output the selected one thereby and wherein said charging unit is adapted to carry out a charge operation to allow the potential on said output terminal set to said initial potential by said initial potential setting unit to rise to a potential of said potential data selected by said analog switches and outputted therefrom thus to carry out output of said potential data.

Claim 4

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said multiplexer includes an initial potential setting unit, analog switches each comprised of a P-channel MOS transistor, and a potential setting unit is adapted to set in advance a potential on an output terminal of said multiplexer to an initial potential lower than potentials of said at least two potential data, wherein said analog switches are adapted so that said potential data are respectively given thereto to select any one of said potential data thereby on a basis of said control signal outputted from said decoder to output the selected one thereby and wherein said charging unit is adapted to carry out a charge operation to allow the potential on said output terminal set to said initial potential by said initial potential setting unit to rise to a potential of said potential data selected by said analog switches and outputted therefrom thus to carry out output of said potential data.

Claim 5

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein there are provided plural sets of said sample-hold circuit, plural sets of said decoder and plural sets of said multiplexer, wherein first sample-hold circuits are further provided respectively in correspondence with said sets of said sample-hold circuit, wherein said first sample-hold circuits are connected to a data bus common thereto to sequentially sample and hold selection data of at least two bits serially transferred by way of said data bus to output the selection data, and wherein said sets of said sample-hold circuit are adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 6

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein there are provided plural sets of said sample-hold circuit, plural sets of said decoder and plural sets of said multiplexer, wherein first sample-hold circuits are further provided respectively in correspondence with said sets of said sample-hold circuit, wherein said first sample-hold circuits are connected to a data bus common thereto to sequentially sample and hold selection data of at least two bits serially transferred by way of said data bus to output the selection data, and wherein said sets of said sample-hold circuit are adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 7

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said output circuit includes a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.

Claim 8

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a decoder adapted so that said selection data outputted from said sample-hold circuit are given thereto to decode said selection data to output control signals; a multiplexer including analog switches adapted so that at least two potential data are respectively given thereto, and adapted so that said control signals outputted from said decoder are given thereto to control operations of said analog switches to select any one of said potential data to output a selected one; and an output circuit adapted so that said potential data selected by said multiplexer and output therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said output circuit includes a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.

Claim 9

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, and analog switches each comprised of a plurality of MOS transistors adapted so that at least two potential data are respectively given thereto; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said MOS transistors to control their ON/OFF operations thus to select and output one of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein there are provided plural sets of said sample-hold circuit and plural sets of said multiplexer, wherein first sample-hold circuits are further provided respectively in correspondence with said sets of said sample-hold circuit, wherein said first sample-hold circuits are connected to a data bus common thereto to sequentially sample and hold selection data of at least two bits serially transferred by way of said data bus to output the selection data, and wherein said sets of said sample-hold circuit are adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 10

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, and analog switches each comprised of a plurality of MOS transistors adapted so that at least two potential data are respectively given thereto; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said MOS transistors to control their ON/OFF operations thus to select and output one of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein there are provided plural sets of said sample-hold circuit and plural sets of said multiplexer, wherein first sample-hold circuits are further provided respectively in correspondence with said sets of said sample-hold circuit, wherein said first sample-hold circuits are connected to a data bus common thereto to sequentially sample and hold selection data of at least two bits serially transferred by way of said data bus to output the selection data, and wherein said sets of said sample-hold circuit are adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 11

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, and analog switches each comprised of a plurality of MOS transistors adapted so that at least two potential data are respectively given thereto; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said MOS transistors to control their ON/OFF operations thus to select and output one of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said output circuit includes a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.

Claim 12

A potential data selection circuit comprising: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, and analog switches each comprised of a plurality of MOS transistors adapted so that at least two potential data are respectively given thereto; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said MOS transistors to control their ON/OFF operations thus to select and output one of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior, wherein said output circuit includes a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.

Claim 13

A potential data selection circuit comprising: a sample-hold circuit for sampling and holding selection data of at least 2 bits to output such data; and a multiplexer including an inversion selection data generation unit, an initial potential setting unit, analog switches each comprised of a plurality of N-channel MOS transistors adapted so that at least two potential data are respectively given thereto, and a discharging unit; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said initial potential setting unit being adapted to set in advance a potential on an output terminal of said multiplexer to an initial potential higher than potentials of said potential data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said N-channel MOS transistors to control their ON/OFF operations, thus to select and output one of said potential data, said discharging unit being operative to carry out a discharge operation to allow a potential on said output terminal set to said initial potential by said initial potential setting unit to fall to a potential of said potential data selected by said analog switches and outputted therefrom to thereby carry out output of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior.

Claim 14

A potential data selection circuit comprising: a sample-hold circuit for sampling and holding selection data of at least 2 bits to output such data; and a multiplexer including an inversion selection data generation unit, an initial potential setting unit, analog switches each comprised of a plurality of N-channel MOS transistors adapted so that at least two potential data are respectively given thereto, and a discharging unit; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said initial potential setting unit being adapted to set in advance a potential on an output terminal of said multiplexer to an initial potential higher than potentials of said potential data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said N-channel MOS transistors to control their ON/OFF operations, thus to select and output one of said potential data, said discharging unit being operative to carry out a discharge operation to allow a potential on said output terminal set to said initial potential by said initial potential setting unit to fall to a potential of said potential data selected by said analog switches and outputted therefrom to thereby carry out output of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior.

Claim 15

A potential data selection circuit as set forth in claim 7, wherein there are provided plural sets of said sample-hold circuit, and plural sets of said multiplexer, wherein first sample-hold circuits further provided respectively in correspondence with said sets of said sample-hold circuit, said first sample-hold circuits being connected to a data bus common thereto to sequentially sample and hold selection data of at least 2 bits serially transferred by way of said data bus to output the selection data, said sets of said sample-hold circuit being adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 16

A potential data selection circuit as set forth in claim 7, wherein said output circuit is a voltage follower amplifier.

Claim 17

A potential data selection circuit as set forth in claim 7, wherein said output circuit comprises a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.

Claim 18

A potential data selection circuit comprising: a sample-hold circuit for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, an initial potential setting unit, analog switches each comprised of a plurality of P-channel MOS transistors adapted so that at least two potential data are respectively given thereto, and a charging unit; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said initial potential setting unit being operative to set in advance a potential on an output terminal of said multiplexer to an initial potential lower than potentials of said potential data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said P-channel MOS transistors to control their ON/OFF operations thus to select and output one of said potential data, said charging unit being operative to carry out a charge operation to allow said potential on said output terminal set to said initial potential by said initial potential setting unit to rise to a potential of said potential data selected by said analog switches and outputted therefrom, thus to provide an output of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior.

Claim 19

A potential data selection circuit comprising: a sample-hold circuit for sampling and holding selection data of at least 2 bits to output such data; a multiplexer including an inversion selection data generation unit, an initial potential setting unit, analog switches each comprised of a plurality of P-channel MOS transistors adapted so that at least two potential data are respectively given thereto, and a charging unit; said inversion selection data generation unit being adapted so that said selection data outputted from said sample-hold circuit are given thereto to generate inversion selection data by inverting said selection data, said initial potential setting unit being operative to set in advance a potential on an output terminal of said multiplexer to an initial potential lower than potentials of said potential data, said analog switches being adapted so that said selection data outputted from said sample-hold circuit and said inversion selection data outputted from said inversion selection data generation unit are given to gates of said P-channel MOS transistors to control their ON/OFF operations thus to select and output one of said potential data, said charging unit being operative to carry out a charge operation to allow said potential on said output terminal set to said initial potential by said initial potential setting unit to rise to a potential of said potential data selected by said analog switches and outputted therefrom, thus to provide an output of said potential data; and an output circuit adapted so that said potential data selected by said multiplexer and outputted therefrom is given thereto to output a signal of a voltage corresponding to said selected potential data to an exterior.

Claim 20

A potential data selection circuit as set forth in claim 11, wherein there are provided plural sets of said sample-hold circuit and plural sets of said multiplexer, wherein first sample-hold circuits are further provided respectively in correspondence with said sets of said sample-hold circuit, said first sample-hold circuits being connected to a data bus common thereto to sequentially sample and hold selection data of at least 2 bits serially transferred by way of said data bus to output the selection data, said sets of said sample-hold circuit being adapted so that said selection data outputted from said first sample-hold circuits are given to said corresponding sets of said sample-hold circuit to hold and output said selection data.

Claim 21

A potential data selection circuit as set forth in claim 11, wherein said output circuit is a voltage follower amplifier.

Claim 22

A potential data selection circuit as set forth in claim 11, wherein said output circuit comprises a first control circuit for allowing current consumption in said output circuit to be small, a second control circuit coupled to said first control circuit for allowing an output of said output circuit to be placed in a high impedance state, an analog switch connecting an output terminal of said multiplexer and an output terminal of said potential data selection circuit, and a third control circuit for controlling said analog switch.