Programmable logic array with reduced product term line voltage swing to speed operation

Claim 2

A programmable logic array for outputting a logic signal previously programmed in synchronization with a clock signal, comprising: logic circuit means (67, 68) comprising a plurality of input lines (48-53), a plurality of product term lines (57-60) each provided intersecting with said input lines, and at least one output line (54, 55) provided intersecting with said plurality of product term lines for outputting a logical product signal by connecting transistors (66, 78, 79) to intersections of said plurality of input lines and any of said plurality of product term lines as required, to be programmed, as well as outputting an logical sum signal by connecting transistors (80, 81) to intersections of said plurality of product term lines and at least one output line, to be programmed, clock gate means (31-34, 39, 40) connected to said plurality of product term lines and said at least one output line, respectively, and responsive to said clock signal to be rendered conductive, and pull-up circuit means (38, 42) comprising first and second conduction terminals and a gate electrode, said first conduction terminal and said gate electrode being connected to power supply terminals (45, 46) and the second conduction terminal being connected to said clock gate means, said pull-up circuit means being responsive to conduction of said clock gate means for precharging said plurality of product term lines and said at least one output line to a potential lower than the power-supply potential.

Claim 3

The programmable logic array according to claim 1, wherein said logic circuit means comprises logical product circuit means (67) comprising first ground lines (61, 62) provided in parallel with each of said product term lines and intersecting with each of said input lines, said transistors being connected to intersections of each of said input lines and each of said product term lines and said first ground line as required, to be programmed, and logical sum circuit means (68) comprising a second ground line (56) provided in parallel with said output line, said transistors being connected to intersections of each of said product term lines and said output line and said second ground line as required, to be programmed.

Claim 4

The programmable logic array according to claim 2, wherein said clock gate means comprises first clock gate means (31-34) each provided corresponding to each of said product term lines and comprising first and second conduction terminals and a gate electrode, the first conduction terminals being connected together to said pull-up circuit means and said second conduction terminals being connected to corresponding product term lines, said first clock gate means being responsive to application of a clock signal of a first level to the gate electrodes for precharging corresponding product term lines, respectively, second clock gate means (35, 36) each provided corresponding to each of said first ground lines and comprising first and second conduction terminals and a gate electrode, said first conduction terminals being connected to one end of said first ground line and said second conduction terminals being grounded, said second clock gate means being responsive to application of a clock signal of a second level to said gate electrodes for grounding said first ground lines, respectively, third clock gate means (39, 40) each provided corresponding said output line and comprising first and second conduction terminals and a gate electrode, said first conduction terminals being connected to said pull-up circuit means and said second conduction terminals being connected to one end of said output line, said third clock gate means being responsive to application of said clock signal of the first level to the gate electrodes for precharging said output line, and fourth clock gate means (41) comprising first and second conduction terminals and a gate electrode, said first conduction terminal being connected to one end of said second ground line and said second conduction terminal being grounded, said fourth clock gate means being responsive to input of said clock signal of the second level to said gate electrode for grounding said second ground line.

Claim 5

The programmable logic array according to claim 3, wherein said pull-up circuit means comprises a first transistor (38) comprising first and second conduction terminals and a gate electrode, said first conduction terminal and said gate electrode being connected to a power supply terminal (45) and said second conduction terminal being connected to first conduction terminals connected together of said first clock gate means, and a second transistor (42) comprising first and second conduction terminals and a gate electrode, said first conduction terminal and said gate electrode being connected to a power supply terminal (46) and said second conduction terminal being connected to first conduction terminals of said third clock gate means.

Claim 6

The programmable logic array according to claim 4, which further comprises fifth clock gate means (43, 44) connected to the other end of said output line and responsive to said clock signal for outputting a signal on said output line.

Claim 7

The programmable logic array according to claim 5, further comprising latch circuit means (11, 12, 14, 15) for storing an output of said fifth clock gate means.