Display electrode substrate

Claim 2

A display electrode substrate comprising a large number of picture element electrodes disposed in a matrix form on an insulating substrate, at least two, first and second, thin film transistors connected to each of said picture element electrodes, gate bus lines provided in parallel to each other between said picture element electrodes, and source bus lines intersecting with said gate bus lines respectively, wherein said first and second thin film transistors are juxtaposed on the same one of said gate bus lines and are connected in series, part of said gate bus line functions as gate electrodes of said first and second thin film transistors, a source electrode of said first thin film transistor is connected to said source bus line, a drain electrode of said first thin film transistor is connected to a source electrode of said second thin film transistor, and a drain electrode of said second thin film transistor is connected to said picture element electrode, and further wherein said drain electrode at said first thin film transistor and said source electrode at said second thin film transistor are positioned in a first row along a longitudinal direction of said gate bus line, and said source electrode at said first thin film transistor and said drain electrode at said second thin film transistor are disposed in a second row along the longitudinal direction of said gate bus line.

Claim 3

A display electrode substrate comprising a large number of picture element electrodes disposed in a matrix form on an insulating substrate, at least two, first and second, thin film transistors connected to each of said picture element electrodes, gate bus lines provided in parallel to each other between said picture element electrodes, and source bus lines intersecting with said gate bus lines respectively, wherein said first and second thin film transistors are juxtaposed on the same one of said gate bus lines and are connected in series, part of said gate bus line functions as gate electrodes of said first and second thin film transistors, a source electrode of said first thin film transistor is connected to said source bus line, a drain electrode of said first thin film transistor is connected to a source electrode of said second thin film transistor, and a drain electrode of said second thin film transistor is connected to said picture element electrode, said source electrode and drain electrode at said first thin film transistor are disposed in a row along a longitudinal direction of said gate bus line, and said source electrode and drain electrode at said second thin film transistor are also disposed in said row. and further wherein said first and second thin film transistors are placed along said gate bus line in such a way as to have said drain electrode of said first thin film transistor situated next to said drain electrode of said second thin film transistor.

Claim 4

A display electrode substrate comprising a large number of picture element electrodes disposed in a matrix form on an insulating substrate, at least two, first and second, thin film transistors connected to each of said picture element electrodes, gate bus lines provided in parallel to each other between said picture element electrodes, and source bus lines intersecting with said gate bus lines respectively, wherein said first and second thin film transistors are juxtaposed on the same one of said gate bus lines and are connected in series, part of said gate bus line functions as gate electrodes of said first and second thin film transistors, a source electrode of said first thin film transistor is connected to said source bus line, a drain electrode of said first thin film transistor is connected to a source electrode of said second thin film transistor, and a drain electrode of said second thin film transistor is connected to said picture element electrode, said source electrode and drain electrode at said first thin film transistor are disposed in a row along a longitudinal direction of said gate bus line, and said source electrode and drain electrode at said second thin film transistor are also disposed in said row. and further wherein said first and second thin film transistors are placed along said gate bus line in such a way as to have said drain electrode of said first thin film transistor situated next to said drain electrode of said second thin film transistor.