Active matrix addressing arrangement for liquid crystal display

Claim 3

The device of claim 1 wherein each said thin film transistor comprises a coplanar poly-Si thin film transistor.

Claim 4

The device of claim 1 wherein each said thin film transistor comprises a staggered poly-Si thin film transistor.

Claim 5

The device of claim 1 wherein each said thin film transistor comprises a staggered amorphous-Si thin film transistor.

Claim 6

The device of claim 1 wherein each said thin film transistor comprises an inverted-staggered amorphous-Si thin film transistor.

Claim 7

The device of claim 1 wherein said commonly shared portion of thin film material is situated in physical alignment with the gate line.

Claim 8

A device as claimed in claim 1 wherein said gates of said first and said second transistors connect to one of said gate branches and said gates of said third and said fourth transistors connect to the other said gate branch.

Claim 9

A matrix display panel for active matrix addressing, said panel having a plurality of gate lines, a plurality of data bus lines and a plurality of pixel electrodes, said gate and data bus lines being transverse with respect to each other, comprising: a plurality of switch devices, each said switch device including first, second, third and fourth thin film transistors, each said transistor having a source and drain, one of said source and drain from each said transistor being electrically directly connected together, said connection being physically a commonly shared portion of thin film material, each said transistor having a gate positioned to act between the respective transistor source and drain, one said gate line being connected to each said gate, a first portion of said gate line being physically split into two electrically parallel branches, said branches separating and coming together in said first gate line portion leaving an open space between said branches, said commonly shared portion of thin film material being positioned in said open space, a first pixel electrode and a second pixel electrode being associated with each said switch device, the first said pixel electrode being physically on one side of said gate line and the second said pixel electrode being on the opposite side of said gate line, the other of said source and drain which is not connected to said commonly shared portion of thin film material of said first transistor and said fourth transistor connect to one said data but line, the other of said source and drain not connected to said commonly shared portion of thin film material of said second transistor being connected to said first pixel electrode, the other of said source and drain not connected to said commonly shared portion of thin film material of said third transistor being connected to said second pixel electrode.

Claim 10

A matrix display panel for active matrix addressing, said panel having a plurality of gate lines, a plurality of data bus lines and a plurality of pixel electrodes, said gate and data bus lines being transverse with respect to each other, comprising: a plurality of switch devices, each said switch device including first, second, third and fourth thin film transistors, each said transistor having a source and drain, one of said source and drain from each said transistor being electrically directly connected together, said connection being physically a commonly shared portion of thin film material, each said transistor having a gate positioned to act between the respective transistor source and drain, one said gate line being connected to each said gate, a first portion of said gate line being physically split into two electrically parallel branches, said branches separating and coming together in said first gate line portion leaving an open space between said branches, said commonly shared portion of thin film material being positioned in said open space, a first pixel electrode and a second pixel electrode being associated with each said switch device, the first said pixel electrode being physically on one side of said gate line and the second said pixel electrode being on the opposite side of said gate line, the other of said source and drain which is not connected to said commonly shared portion of thin film material of said first transistor and said fourth transistor connect to one said data but line, the other of said source and drain not connected to said commonly shared portion of thin film material of said second transistor being connected to said first pixel electrode, the other of said source and drain not connected to said commonly shared portion of thin film material of said third transistor being connected to said second pixel electrode.

Claim 11

The panel of claim 8 wherein each said thin film transistor comprises a coplanar poly-Si thin film transistor.

Claim 12

The panel of claim 8 wherein each said thin film transistor comprises a staggered poly-Si thin film transistor.

Claim 13

The panel of claim 8 wherein each said thin film transistor comprises a staggered amorphous-Si thin film transistor.

Claim 14

The panel of claim 8 wherein each said thin film transistor comprises an inverted-staggered amorphous-Si thin film transistor.

Claim 15

The panel of claim 8 wherein said commonly shared portion of thin film material is situated in physical alignment with the gate line.

Claim 16

A matrix display panel as claimed in claim 8, wherein said connections to said data bus line are on opposite sides physically of said one gate line.

Claim 17

A device as claimed in claim 8 wherein said gates of said first and said second transistors connect to one said gate branch and said gates of said third and said fourth transistors connect to the other said gate branch.

Claim 18

An addressing circuit for an LCD display, said display having a plurality of display electrodes arranged in vertical columns and horizontal rows, a grid of gate lines positioned between adjacent electrode rows and data lines positioned between adjacent electrode columns, comprising: a first, second, third and a fourth thin film transistor, each said transistor having a source, drain and gate electrode; connective means for electrically connecting the sources of said first and fourth transistors to the same adjacent data line, the drains of said first and fourth transistors being electrically connected at a common junction; connective means for electrically connecting the drains of said second and third transistors respectively to adjacent display electrodes, said adjacent display electrodes being in the same column, one said gate line being positioned intermediate said adjacent electrodes, the sources of said second and third transistors being electrically connected at said common junction; and connective means for connecting the gates of said four transistors to said intermediate gate line.

Claim 19

An addressing circuit for an LCD display, said display having a plurality of display electrodes arranged in vertical columns and horizontal rows, a grid of gate lines positioned between adjacent electrode rows and data lines positioned between adjacent electrode columns, comprising: a first, second, third and a fourth thin film transistor, each said transistor having a source, drain and gate electrode; connective means for electrically connecting the sources of said first and fourth transistors to the same adjacent data line, the drains of said first and fourth transistors being electrically connected at a common junction; connective means for electrically connecting the drains of said second and third transistors respectively to adjacent display electrodes, said adjacent display electrodes being in the same column, one said gate line being positioned intermediate said adjacent electrodes, the sources of said second and third transistors being electrically connected at said common junction; and connective means for connecting the gates of said four transistors to said intermediate gate line.

Claim 20

An addressing circuit as claimed in claim 16 wherein said intermediate gate line is physically split over a portion of its length into two electrically parallel branches, said branches separating and coming together in said length of said gate line portion leaving an open space therebetween, the gate electrodes of said first and second transistors being connected to one said branch and the gate electrodes of said third and fourth transistors being connected to the other said branch, said branches overlaying and crossing said respectively connected transistors between the sources and drains thereof.