Process for forming a semiconductor device having a capacitor

Claim 1

A process for formation of a semiconductor memory cell, comprising: (1) depositing an insulating inter-layer after forming circuit elements including transistors and memory access transistors each having source/drain regions upon a silicon substrate, opening a bit line contact, depositing a doped polysilicon layer, etching back the doped polysilicon layer to form a polysilicon plug in the bit line contact, depositing a tungsten polycide, and patterning the tungsten polycide to form a bit line connected to the polysilicon plug; (2) depositing an insulating inter-layer and flattening the insulating inter-layer, opening a contact hole to a word line and a contact hole to a source/drain region of a transistor to be connected to a primary metallization wiring layer, depositing a refractory metal or metal compound, and patterning the refractory metal or metal compound to form the primary metallization wiring; (3) depositing and flattening an oxide layer, and depositing an insulating layer having an etch selectivity higher than that of the oxide layer; (4) opening a contact hole of a buried contact for connecting a source/drain region of one of the memory access transistors to a storage electrode of a storage capacitor, depositing an oxide layer thereupon, and etching the oxide layer to a depth greater than the thickness of the oxide layer in order to form a oxide side wall in the contact hole; (5) depositing a polysilicon layer and patterning the polysilicon layer to form a storage electrode, removing the high etch selectivity insulating layer by wet etching, and forming a dielectric layer on the surface of the storage electrode of capacitor; and (6) depositing and patterning a plate polysilicon layer, depositing an insulating layer thereupon, and forming a secondary metallization wiring on the insulating layer.

Claim 5

A method for making a semiconductor device, comprising the steps of: forming an active region and a field region on a semiconductor substrate; forming a word line on the semiconductor substrate and first and second impurity regions on the sides of the word line in the active region; forming a first insulating layer on the semiconductor substrate; forming a first contact hole on the first impurity region; forming a bit line connecting the first impurity region through the first contact hole; forming a second insulating layer on the bit line and the first insulating layer; forming a second contact hole on the word line and forming a wiring layer connected to the word line through the second contact hole; forming a third insulating layer on the wiring layer and the second insulating layer; forming a third contact hole on the second impurity regions; forming a conductive layer on the third insulating layer and the third contact hole; forming a storage electrode on the third contact hole by a selective etch; and forming a dielectric layer and a plate electrode on the storage electrode.

Claim 6

A method for making a semiconductor device, comprising the steps of: forming an active region and a field region on a semiconductor substrate; forming a word line on the semiconductor substrate and first and second impurity regions on the sides of the word line in the active region; forming a first insulating layer on the semiconductor substrate; forming a first contact hole on the first impurity region; forming a bit line connecting the first impurity region through the first contact hole; forming a second insulating layer on the bit line and the first insulating layer; forming a second contact hole on the word line and forming a wiring layer connected to the word line through the second contact hole; forming a third insulating layer on the wiring layer and the second insulating layer; forming a third contact hole on the second impurity regions; forming a conductive layer on the third insulating layer and the third contact hole; forming a storage electrode on the third contact hole by a selective etch; and forming a dielectric layer and a plate electrode on the storage electrode.

Claim 15

A method for making a semiconductor device, comprising the steps of: forming an active region and a field region on a semiconductor substrate; forming a word line on the semiconductor substrate and first and second impurity regions on the sides of the word line in the active region; forming a first insulation layer on the active region and the field region; forming a first contact hole on the first impurity region; forming a bit line connecting the first impurity region through the first contact hole; forming a second insulating layer on the bit line and the first insulating layer; forming a second contact hole on the word line and forming a wiring layer connected to the word line through the second contact hole; forming a third insulating layer and a fourth insulating layer on the wiring layer and the second insulation layer; opening a third contact hole on the second impurity region; forming an insulating side wall spacer along the inner sides of the third contact hole; forming a conductive layer on the fourth insulating layer and the third contact hole; forming a storage electrode over the third contact hole by patterning the conductive layer; wet etching the fourth insulating layer; and forming a dielectric layer and a plate electrode on the storage electrode.

Claim 16

A method for making a semiconductor device, comprising the steps of: forming an active region and a field region on a semiconductor substrate; forming a word line on the semiconductor substrate and first and second impurity regions on the sides of the word line in the active region; forming a first insulation layer on the active region and the field region; forming a first contact hole on the first impurity region; forming a bit line connecting the first impurity region through the first contact hole; forming a second insulating layer on the bit line and the first insulating layer; forming a second contact hole on the word line and forming a wiring layer connected to the word line through the second contact hole; forming a third insulating layer and a fourth insulating layer on the wiring layer and the second insulation layer; opening a third contact hole on the second impurity region; forming an insulating side wall spacer along the inner sides of the third contact hole; forming a conductive layer on the fourth insulating layer and the third contact hole; forming a storage electrode over the third contact hole by patterning the conductive layer; wet etching the fourth insulating layer; and forming a dielectric layer and a plate electrode on the storage electrode.